Fix for Intel Arrow Lake CPUs

kimwalisch · Nov 5, 2024 · 22f4d80 · 22f4d80
1 parent e980bca
commit 22f4d80
Showing 1 changed file with 7 additions and 0 deletions.
diff --git a/src/CpuInfo.cpp b/src/CpuInfo.cpp
@@ -689,6 +689,13 @@ void CpuInfo::init()
       if (level >= 1 &&
           level <= 3)
       {
+        // Intel Arrow Lake CPUs have two L1 data caches. These
+        // caches are ordered from fastest to slowest. Since we are
+        // interested in the fastest L1 data cache, we only store
+        // the information about the first L1 data cache we find.
+        if (cacheSizes_[level] != 0)
+          continue;
+
         std::string type = path + "/type";
         std::string cacheType = getString(type);