a Python framework for managing embedded HW/SW projects

Make great analog designs

Scala based HDL

UART 16550 core

PyTorch Brevitas Quantization

System-on-Chip for In-Silicon Verification of IP Cores

Yosys Open SYnthesis Suite

A DDR3 memory controller in Verilog for various FPGAs

DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.

Running Linux on IOb-SoC-OpenCryptoHW

Basic Verilog Ethernet core and C driver functions

Reconfigurable Hardware-Accelerated Open-Source Cryptographic IP Cores

A FPGA friendly 32 bit RISC-V CPU implementation

Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage …

RISC-V System on Chip Template

libmad library

MPEG Audio Layer 2 (MP2) encoder

Tiny, fast, non-dependent and fully loaded printf implementation for embedded systems. Extensive test suite passing.

SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.

Python script to transform a VCD file to wavedrom format

Verilog Configurable Cache

IOb_SoC version of the Picorv32 RISC-V Verilog IP core

Verilog AXI components for FPGA implementation

Verilog AXI components for FPGA implementation

Coarse Grained Reconfigurable Array

PicoRV32 - A Size-Optimized RISC-V CPU