risc-y

Six-stage processor supporting the RV32I instruction set, written from scratch in Bluespec. Final design project submission for MIT 6.004, and a continuous work in progress since.

Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
expected		expected
sw		sw
ALU.bsv		ALU.bsv
BTB.bsv		BTB.bsv
CAU.bsv		CAU.bsv
Cache.bsv		Cache.bsv
CacheTypes.bsv		CacheTypes.bsv
Common.bsv		Common.bsv
DRAM.bsv		DRAM.bsv
Decode.bsv		Decode.bsv
Ehr.bsv		Ehr.bsv
Execute.bsv		Execute.bsv
Makefile		Makefile
MemorySystem.bsv		MemorySystem.bsv
MemoryTypes.bsv		MemoryTypes.bsv
ProcTypes.bsv		ProcTypes.bsv
ProcessorFourWIP.bsv		ProcessorFourWIP.bsv
ProcessorIPC.bsv		ProcessorIPC.bsv
ProcessorRuntime.bsv		ProcessorRuntime.bsv
ProcessorThree.bsv		ProcessorThree.bsv
ProjectDefs.bsv		ProjectDefs.bsv
README.md		README.md
RFile.bsv		RFile.bsv
RWBramCore.bsv		RWBramCore.bsv
SFifo.bsv		SFifo.bsv
SRAM6004.bsv		SRAM6004.bsv
ScheduleMonitor.bsv		ScheduleMonitor.bsv
Scoreboard.bsv		Scoreboard.bsv
base.csv		base.csv
bench.csv		bench.csv
grade.sh		grade.sh
hiddenImports.bsv		hiddenImports.bsv
hiddenMemory.bsv		hiddenMemory.bsv
test.sh		test.sh

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