Add SAM4L FLASHCALW header file

nuttx/arch/arm/src/sam34/Make.defs

@@ -77,16 +77,15 @@ endif
 # Required SAM3/4 files
 
 CHIP_ASRCS  =
-CHIP_CSRCS  = sam_allocateheap.c sam_clockconfig.c sam_gpioirq.c
-CHIP_CSRCS += sam_irq.c sam_lowputc.c sam_serial.c sam_start.c
-CHIP_CSRCS += sam_timerisr.c
+CHIP_CSRCS  = sam_allocateheap.c sam_gpioirq.c sam_irq.c sam_lowputc.c
+CHIP_CSRCS += sam_serial.c sam_start.c sam_timerisr.c
 
 # Configuration-dependent SAM3/4 files
 
 ifeq ($(CONFIG_ARCH_CHIP_SAM4L),y)
-CHIP_CSRCS += sam4l_gpio.c
+CHIP_CSRCS += sam4l_clockconfig.c sam4l_gpio.c
 else
-CHIP_CSRCS += sam3u_gpio.c
+CHIP_CSRCS += sam3u_clockconfig.c sam3u_gpio.c
 endif
 
 ifeq ($(CONFIG_NUTTX_KERNEL),y)

nuttx/arch/arm/src/sam34/chip/sam_eefc.h → nuttx/arch/arm/src/sam34/chip/sam3u_eefc.h

@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam_eefc.h
+ * arch/arm/src/sam34/chip/sam3u_eefc.h
  *
  *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <[email protected]>
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_EEFC_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_EEFC_H
+#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_EEFC_H
+#define __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_EEFC_H
 
 /****************************************************************************************
  * Included Files
@@ -117,4 +117,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_EEFC_H */
+#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_EEFC_H */

nuttx/arch/arm/src/sam34/chip/sam_supc.h → nuttx/arch/arm/src/sam34/chip/sam3u_supc.h

@@ -1,5 +1,5 @@
 /****************************************************************************************
- * arch/arm/src/sam34/chip/sam_supc.h
+ * arch/arm/src/sam34/chip/sam3u_supc.h
  *
  *   Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <[email protected]>
@@ -33,8 +33,8 @@
  *
  ****************************************************************************************/
 
-#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_SUPC_H
-#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_SUPC_H
+#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_SUPC_H
+#define __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_SUPC_H
 
 /****************************************************************************************
  * Included Files
@@ -161,4 +161,4 @@
  * Public Functions
  ****************************************************************************************/
 
-#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_SUPC_H */
+#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_SUPC_H */

nuttx/arch/arm/src/sam34/chip/sam4l_memorymap.h

@@ -109,7 +109,7 @@
 
 #define SAM_FLASHCALW_BASE   0x400a0000 /* 0x400a0000-0x400a03ff: FLASHCALW */
 #define SAM_PICOCACHE_BASE   0x400a0400 /* 0x400a0400-0x400a0fff: PICOCACHE */
-#define SAM_HMATRIX_BASE     0x400a1000 /* 0x400a1000-0x400a1fff: PICOCACHE */
+#define SAM_HMATRIX_BASE     0x400a1000 /* 0x400a1000-0x400a1fff: HMATRIX */
 #define SAM_PDCA_BASE        0x400a2000 /* 0x400a2000-0x400a2fff: Peripheral DMA Controller */
 #define SAM_SMAP_BASE        0x400a3000 /* 0x400a3000-0x400a3fff: SMAP */
 #define SAM_CRCCU_BASE       0x400a4000 /* 0x400a4000-0x400a4fff: CRC Calculation Unit */

nuttx/arch/arm/src/sam34/sam_clockconfig.c → nuttx/arch/arm/src/sam34/sam3u_clockconfig.c

@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/arm/src/chip/sam_clockconfig.c
+ * arch/arm/src/chip/sam3u_clockconfig.c
  *
  *   Copyright (C) 2010 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <[email protected]>
@@ -50,9 +50,9 @@
 
 #include "sam_clockconfig.h"
 #include "chip/sam_pmc.h"
-#include "chip/sam_eefc.h"
+#include "chip/sam3u_eefc.h"
 #include "chip/sam_wdt.h"
-#include "chip/sam_supc.h"
+#include "chip/sam3u_supc.h"
 #include "chip/sam_matrix.h"
 
 /****************************************************************************

nuttx/arch/avr/src/at32uc3/at32uc3_flashc.h

@@ -89,12 +89,12 @@
 #define FLASHC_FSR_QPRR             (1 << 5)  /* Bit 5:  Quick Page Read Result */
 #define FLASHC_FSR_FSZ_SHIFT        (13)      /* Bits 13-15: Flash Size */
 #define FLASHC_FSR_FSZ_MASK         (7 << FLASHC_FSR_FSZ_SHIFT)
-#  define FLASHC_FSR_FSZ_23KB       (0 << FLASHC_FSR_FSZ_SHIFT) /* 32 Kbytes */
+#  define FLASHC_FSR_FSZ_32KB       (0 << FLASHC_FSR_FSZ_SHIFT) /* 32 Kbytes */
 #  define FLASHC_FSR_FSZ_64KB       (1 << FLASHC_FSR_FSZ_SHIFT) /* 64 Kbytes */
 #  define FLASHC_FSR_FSZ_128KB      (2 << FLASHC_FSR_FSZ_SHIFT) /* 128 Kbytes */
 #  define FLASHC_FSR_FSZ_256KB      (3 << FLASHC_FSR_FSZ_SHIFT) /* 256 Kbytes */
 #  define FLASHC_FSR_FSZ_384KB      (4 << FLASHC_FSR_FSZ_SHIFT) /* 384 Kbytes */
-#  define FLASHC_FSR_FSZ_512KGB     (5 << FLASHC_FSR_FSZ_SHIFT) /* 512 Kbytes */
+#  define FLASHC_FSR_FSZ_512KB      (5 << FLASHC_FSR_FSZ_SHIFT) /* 512 Kbytes */
 #  define FLASHC_FSR_FSZ_768KB      (6 << FLASHC_FSR_FSZ_SHIFT) /* 768 Kbytes */
 #  define FLASHC_FSR_FSZ_1MB        (7 << FLASHC_FSR_FSZ_SHIFT) /* 1024 Kbytes */
 #define FLASHC_FSR_LOCK(n)          (1 << ((n)+16)

nuttx/configs/sam4l-xplained/include/board.h

@@ -78,6 +78,14 @@
 
 #define BOARD_CKGR_UCKR_UPLLCOUNT (3 << CKGR_UCKR_UPLLCOUNT_SHIFT)
 
+/* System clock dividers: Fbus = Fsys / (2 ^ BUS_div) */
+
+#define BOARD_SYSCLK_CPU_DIV       0
+#define BOARD_SYSCLK_PBA_DIV       0
+#define BOARD_SYSCLK_PBB_DIV       0
+#define BOARD_SYSCLK_PBC_DIV       0
+#define BOARD_SYSCLK_PBD_DIV       0
+
 /* Resulting frequencies */
 
 #define SAM_MAINOSC_FREQUENCY      (12000000)