An implementation of 8x8 systolic array written in Verilog, compatible to synthesize with Vivado 2023.01. You should create a wrapper module for matmul_system.v and create a block diagram connecting PS and 4 BRAMs corresponsing to SP, Activation, Weight, and Output.
-
Notifications
You must be signed in to change notification settings - Fork 0
izaazm/Systolic-Array
Folders and files
| Name | Name | Last commit message | Last commit date | |
|---|---|---|---|---|
Repository files navigation
About
An implementation of 8x8 systolic array written in Verilog, compatible to synthesize with Vivado 2023.01
Resources
Stars
Watchers
Forks
Releases
No releases published
Packages 0
No packages published