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3. [Triton] Language and Runtime

Open
Due by July 4, 2025
Last updated Jun 5, 2025
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  • FAILED language\test_core.py::test_histogram[8-512] on BMG, Windows

    ci
    hw: bmg
    tests: ut
    windows
    Status: Open.
    Bug
    #3983 In intel/intel-xpu-backend-for-triton;
    · pbchekin opened on Apr 23, 2025

  • [TEST] Fix <code>test_matmul.py</code> failures

    tests: ut
    Status: Open.
    Bug
    #3307 In intel/intel-xpu-backend-for-triton;
    · whitneywhtsang opened on Jan 30, 2025

  • [Profiler] Enable Triton Proton for the Intel GPU's

    performance
    Status: Open.
    Epic
    #1145 In intel/intel-xpu-backend-for-triton;
    · chengjunlu opened on May 17, 2024

  • Remove uses of 'distutils'

    packaging
    Status: Open.
    Bug
    #3630 In intel/intel-xpu-backend-for-triton;
    · sommerlukas opened on Mar 7, 2025

  • [Triton-RAISE-BP] New look at pointer raising: opportunities and blockers

    codegen: mlir
    performance
    research
    upstream: triton
    Status: Open.
    Epic
    #2587 In intel/intel-xpu-backend-for-triton;
    · mfrancepillois opened on Oct 29, 2024

  • [RAISE-BP] Safely handle masks and modulo ops

    codegen: mlir
    performance
    Status: Open.
    Feature
    #1784 In intel/intel-xpu-backend-for-triton;
    · mfrancepillois opened on Aug 5, 2024

  • Remove workaround on <code>AbsFOpConversion</code> with <code>bf16</code>

    dependencies: spirv_translator
    Status: Open.
    Feature
    #1229 In intel/intel-xpu-backend-for-triton;
    · whitneywhtsang opened on Jun 2, 2024

  • Consume a bitcode library for math and other functions from sycl runtime

    codegen: mlir
    dependencies: sycl runtime
    Status: Open.
    Feature
    #240 In intel/intel-xpu-backend-for-triton;
    · kurapov-peter opened on Jan 11, 2024

  • support constrained floating point intrinsics when attribute <code>strictfp</code> marked

    tests: ut
    Status: Open.
    Feature
    #871 In intel/intel-xpu-backend-for-triton;
    · ESI-SYD opened on Apr 15, 2024

  • Lowering <code>arith::TruncFOp</code> from fp32 to bf16 is harder than it should be.

    accuracy
    codegen: spirv
    Status: Open.
    Feature
    #1111 In intel/intel-xpu-backend-for-triton;
    · FMarno opened on May 13, 2024

  • [Bug] There is bug in scratchpad space allocation in SLM and calling convention of no-inlined tt.fucn with scratch space.

    codegen: mlir
    Status: Open.
    Bug
    #1697 In intel/intel-xpu-backend-for-triton;
    · chengjunlu opened on Jul 25, 2024

  • Investigate using OCL's atomic functions for AtormicCAS and AtomicRMW codegen.

    codegen: mlir
    research
    Status: Open.
    #1882 In intel/intel-xpu-backend-for-triton;
    · etiotto opened on Aug 14, 2024

  • The Intel Triton runtime enumerates the sycl devices list which maybe not consistent with the Torch runtime.

    research
    Status: Open.
    Bug
    #1916 In intel/intel-xpu-backend-for-triton;
    · chengjunlu opened on Aug 19, 2024

  • Support true fp32 matmul

    codegen: gemm
    Status: Open.
    Feature
    #1956 In intel/intel-xpu-backend-for-triton;
    · ZzEeKkAa opened on Aug 20, 2024

  • Dot op verifier should verify that dpas layout encoding and element type are aligned

    codegen: dpas
    performance
    Status: Open.
    Feature
    #990 In intel/intel-xpu-backend-for-triton;
    · LiyangLingIntel opened on Apr 28, 2024

  • SPIR-V Reproducer: Support data types - float8e5 and float8e4nv

    Status: Open.
    Feature
    #2666 In intel/intel-xpu-backend-for-triton;
    · kballeda opened on Nov 11, 2024

  • Consider reusing PyTorch solution for <code>ext_oneapi_get_default_context</code>

    Status: Open.
    Feature
    #2757 In intel/intel-xpu-backend-for-triton;
    · anmyachev opened on Nov 19, 2024

  • SPIRVRunner: Investigate and handle multi-kernel execution (benchmark- gemm_streamk_benchmark.py)

    research
    Status: Open.
    Feature
    #2831 In intel/intel-xpu-backend-for-triton;
    · kballeda opened on Nov 26, 2024

  • Compare microkernel benchmark IR against main for PRs

    ci
    codegen: mlir
    upstream: rebasePR to be up-streamed
    Status: Open.
    Epic
    #2974 In intel/intel-xpu-backend-for-triton;
    · alexbaden opened on Dec 10, 2024

  • Evaluate new IGC <code>ManageableBarriers</code>

    dependencies: igc
    research
    Status: Open.
    Task
    #3093 In intel/intel-xpu-backend-for-triton;
    · whitneywhtsang opened on Jan 6, 2025

  • SPIR-V Reproducer: Handle test specific features such as add-cols, add-rows handling for "test_dot"

    Status: Open.
    Feature
    #2667 In intel/intel-xpu-backend-for-triton;
    · kballeda opened on Nov 11, 2024

  • Replace SPIR-V translator with LLVM SPIR-V backend

    dependencies: spirv_translator
    Status: Open.
    Epic
    #3246 In intel/intel-xpu-backend-for-triton;
    · kurapov-peter opened on Jan 23, 2025

  • Compare SPIR-V backend and SPIR-V translator latencies

    dependencies: spirv_translator
    research
    Status: Open.
    Task
    #3249 In intel/intel-xpu-backend-for-triton;
    · kurapov-peter opened on Jan 23, 2025

  • Evaluate e2e performance impact of using LLVM SPIR-V backend

    dependencies: spirv_translator
    performance
    research
    tests: e2e
    Status: Open.
    Task
    #3250 In intel/intel-xpu-backend-for-triton;
    · kurapov-peter opened on Jan 23, 2025

  • Reduce code duplication in <code>benchmark_testing</code>

    code quality
    Status: Open.
    #3160 In intel/intel-xpu-backend-for-triton;
    · anmyachev opened on Jan 14, 2025
    •