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Commit 9378bc3

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Gang Y Chenigcbot
authored andcommitted
move scratch surface creation to IGC
fix ip scanning issue
1 parent fe771f7 commit 9378bc3

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2 files changed

+70
-29
lines changed

2 files changed

+70
-29
lines changed

IGC/Compiler/CISACodeGen/CISABuilder.cpp

Lines changed: 60 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -3366,10 +3366,68 @@ namespace IGC
33663366
V(vKernel->GetPredefinedSurface(surfacevar, PREDEFINED_SURFACE_T255));
33673367
break;
33683368
case ESURFACE_SCRATCH:
3369-
// NOTE: For scratch surface, we need to shr the surface state offset coming in R0.5 by 4.
3370-
// This shr operation is generated by vISA in HDC path
3369+
{
3370+
// For scratch surface, we need to shr the surface state offset coming in R0.5 by 4
3371+
// This is because the scratch offset is passed in via r0.5[31:10],
3372+
// but the BSS/SS descriptor expects the offset in [31:6] bits, thus we must shift it right by 4
3373+
// We also need to and r0.5 with 0xFFFFFC00 to retrieve bits 31:10
3374+
3375+
// TBD is it needed or we will have the bits 9:0 are reset already in the payload?
3376+
// (W) and (1) sso r0.5 0xFFFFC00, placed at kernel entry
3377+
VISA_GenVar* r0Var = nullptr;
3378+
VISA_VectorOpnd* surfOpnd_r0_5 = nullptr;
3379+
uint32_t imm_data_dw = 0xFFFFFC00;
3380+
VISA_VectorOpnd* andOpnd = nullptr;
3381+
VISA_VectorOpnd* surfOpAndDst = nullptr;
3382+
33713383
V(vKernel->GetPredefinedSurface(surfacevar, PREDEFINED_SURFACE_SCRATCH));
3384+
V(vKernel->GetPredefinedVar(r0Var, PREDEFINED_R0));
3385+
3386+
CVariable* surfOpAndVar = m_program->GetNewVariable(1, ISA_TYPE_UD, EALIGN_DWORD, true, "SurfaceOpnd");
3387+
V(vKernel->CreateVISADstOperand(surfOpAndDst, GetVISAVariable(surfOpAndVar), 1, 0, 0));
3388+
3389+
V(vKernel->CreateVISASrcOperand(surfOpnd_r0_5, r0Var, MODIFIER_NONE, 0, 1, 0, 0, 5));
3390+
V(vKernel->CreateVISAImmediate(andOpnd, &imm_data_dw, ISA_TYPE_UD));
3391+
V(vKernel->AppendVISAArithmeticInst(
3392+
ISA_AND,
3393+
nullptr,
3394+
false,
3395+
vISA_EMASK_M1_NM,
3396+
EXEC_SIZE_1,
3397+
surfOpAndDst,
3398+
surfOpnd_r0_5,
3399+
andOpnd));
3400+
3401+
// if use new extend message descriptor format
3402+
// (W) shr (1) a0.0 ss0 0x4
3403+
// else
3404+
// (W) shl (1) a0.0 ss0 0x2
3405+
3406+
VISA_VectorOpnd* surfOpndShiftDst = nullptr;
3407+
VISA_VectorOpnd* surfOpnd_r0_5_bits_31_10 = nullptr;
3408+
VISA_VectorOpnd* shiftOpnd = nullptr;
3409+
bool useNewExtMsgFormat = m_program->m_Platform->hasScratchSurface();
3410+
// Not sure that we have a case of using bindless scratch surface on
3411+
// platforms that use old ExtMsgFormat a0[12:31] as surface-state
3412+
// heap offset. However, the logic is maintained when moving from
3413+
// finalizer to IGC
3414+
uint16_t imm_data_w = useNewExtMsgFormat ? 4 : 2;
3415+
ISA_Opcode shiftOpcode = useNewExtMsgFormat ? ISA_SHR : ISA_SHL;
3416+
3417+
surfOpnd_r0_5_bits_31_10 = GetSourceOperandNoModifier(surfOpAndVar);
3418+
V(vKernel->CreateVISAImmediate(shiftOpnd, &imm_data_w, ISA_TYPE_UW));
3419+
V(vKernel->CreateVISAStateOperand(surfOpndShiftDst, surfacevar, 0, true));
3420+
V(vKernel->AppendVISAArithmeticInst(
3421+
shiftOpcode,
3422+
nullptr,
3423+
false,
3424+
vISA_EMASK_M1_NM,
3425+
EXEC_SIZE_1,
3426+
surfOpndShiftDst,
3427+
surfOpnd_r0_5_bits_31_10,
3428+
shiftOpnd));
33723429
break;
3430+
}
33733431
default:
33743432
IGC_ASSERT_MESSAGE(0, "Invalid surface");
33753433
break;
@@ -7304,8 +7362,6 @@ namespace IGC
73047362
// For scratch surface, we need to shr the surface state offset coming in R0.5 by 4
73057363
// This is because the scratch offset is passed in via r0.5[31:10],
73067364
// but the BSS/SS descriptor expects the offset in [31:6] bits, thus we must shift it right by 4
7307-
7308-
// NOTE: This shr operation is generated by IGC in LSC path, where as in HDC path it is done by vISA
73097365
VISA_GenVar* r0Var = nullptr;
73107366
V(vKernel->GetPredefinedVar(r0Var, PREDEFINED_R0));
73117367
VISA_VectorOpnd* surfOpnd = nullptr;

visa/BuildIRImpl.cpp

Lines changed: 10 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -1867,41 +1867,26 @@ G4_INST* IR_Builder::createInternalBfnInst(
18671867
return ii;
18681868
}
18691869

1870-
//scratch surfaces, write r0.5 to message descriptor
1871-
//exdesc holds the value of the extended message descriptor for bit [0:11]
1872-
// kernel entry:
1873-
// and (1) tmp<1>:ud r0.5<0;1,0>:ud 0xFFFFFC00:ud {NoMask}
1874-
// before send message:
1875-
// shl (1) a0.0<1>:ud tmp<1>:ud 0x2 {NoMask}
1876-
// (for old exDesc format) add (1) a0.0<1>:ud tmp<1>:ud exDesc:ud {NoMask}
1877-
// returns a0.0<0;1,0>:ud
1870+
// scratch surfaces, write the content of T251 to extended message descriptor
1871+
// exdesc holds the value of the extended message descriptor for bit [0:11]
1872+
// add (1) a0.2<1>:ud T251<1>:ud exDesc:ud {NoMask}
1873+
// returns a0.2<0;1,0>:ud
18781874
G4_SrcRegRegion* IR_Builder::createScratchExDesc(uint32_t exdesc)
18791875
{
1876+
// virtual var for each exdesc
1877+
G4_SrcRegRegion* T251 = createSrcRegRegion(builtinScratchSurface, getRegionScalar());
18801878
const char* buf = getNameString(mem, 20, "ExDesc%d", num_temp_dcl++);
18811879
G4_Declare* exDescDecl = createDeclareNoLookup(buf, G4_ADDRESS, 1, 1, Type_UD);
18821880
exDescDecl->setSubRegAlign(Four_Word);
18831881

1884-
// copy r0.5[10:31] to a0[12:31] or a0[6:31] for the new format
1885-
initScratchSurfaceOffset();
1886-
1887-
if (!useNewExtDescFormat())
1882+
G4_DstRegRegion* dst = createDstRegRegion(exDescDecl, 1);
1883+
if (useNewExtDescFormat())
18881884
{
1889-
1890-
// (W) shl (1) a0.0 sso 0x2
1891-
auto shlSrc0 = createSrcRegRegion(scratchSurfaceOffset, getRegionScalar());
1892-
auto shlDst = createDstRegRegion(exDescDecl, 1);
1893-
createBinOp(G4_shl, g4::SIMD1, shlDst, shlSrc0, createImm(0x2, Type_UW), InstOpt_WriteEnable, true);
1894-
1895-
G4_DstRegRegion* dst = createDstRegRegion(exDescDecl, 1);
1896-
createBinOp(G4_add, g4::SIMD1, dst, createSrcRegRegion(exDescDecl, getRegionScalar()),
1897-
createImm(exdesc, Type_UD), InstOpt_WriteEnable, true);
1885+
createMov(g4::SIMD1, dst, T251, InstOpt_WriteEnable, true);
18981886
}
18991887
else
19001888
{
1901-
// (W) shr (1) a0.0 ss0 0x4
1902-
auto shrSrc0 = createSrcRegRegion(scratchSurfaceOffset, getRegionScalar());
1903-
auto shrDst = createDstRegRegion(exDescDecl, 1);
1904-
createBinOp(G4_shr, g4::SIMD1, shrDst, shrSrc0, createImm(0x4, Type_UW), InstOpt_WriteEnable, true);
1889+
createBinOp(G4_add, g4::SIMD1, dst, T251, createImm(exdesc, Type_UD), InstOpt_WriteEnable, true);
19051890
}
19061891
return createSrcRegRegion(exDescDecl, getRegionScalar());
19071892
}

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