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Add CS4223 midterms
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indocomsoft committed Oct 7, 2019
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CS4223 Finals Cheatsheet v1.0 (\today)\\
by~Julius Putra Tanu Setiaji,~page~\thepage~of~\pageref{LastPage}
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\scriptsize
\begin{multicols*}{4}
\raggedcolumns
\section{Data Dependencies}
\begin{itemize}
\item \textbf{True Dep} = RAW
\item \textbf{Anti Dep} = WAR
\item \textbf{Output Dep} = WAW
\end{itemize}
\section{Cache}
\subsection{Memory Access Time}
\textbf{Hit rate}, \textbf{Hit time} = cache access time, \textbf{miss rate} = 1 - hit rate, \textbf{miss penalty} = time to replace block cache + hit time\\
\textbf{Average access time} = hit rate $\times$ hit time + miss rate $\times$ miss penalty.
\subsection{Write Policy}
\begin{itemize}
\item \textbf{Write-through}, write data both to the cache \& main memory. Problem: write will operate at speed of main memory. Solution: write buffer b/w cache and main memory.
\item \textbf{Write-back} cache, only write to cache, write to main memory only when cache block is replaced (evicted). Problem: wasteful to write back every evicted cache. Solution: Use a "dirty bit" if cache content is changed. Write back only if dirty bit is set.
\end{itemize}
\subsection{Types of Cache Misses}
\textbf{Compulsory misses} on first access to a block, \textbf{Conflict misses} on collision, \textbf{Capacity misses} when blocks are discarded as cache is full
\subsection{Handling Cache Misses}
Read Miss: load data from memory to cache and then to register.
Write miss:
\begin{itemize}
\item \textbf{Write-allocate}: load complete block to cache, change the required word in cache, write to main memory (write policy).
\item \textbf{Write-around}: no loading to cache, write to main memory only
\end{itemize}
\subsection{Direct Mapped Cache \textmd{ -- (index, valid, tag)}}
\textbf{How to id}: tag match with only 1 block.\\
\textbf{Cache block size} = $2^N$ bytes, \textbf{no of cache blocks} = $2^M$\\
\textbf{Offset} = $N$ bits, \textbf{Index} = $M$ bits, \textbf{Tag} = $32 - (N+M)$ bits
\subsection{N-way Set Associative Cache}
\textbf{How to id}: tag match for all the blocks within the set.\\
A block maps to a unique set (each set having $n$ "cache blocks")\\
\textbf{Cache block size} = $2^N$ bytes, \textbf{no of cache blocks} = $\frac{\text{size of cache}}{\text{size of block}}$,\\
\textbf{no of sets} = $\frac{\text{no of blocks}}{\text{n in n-way}}$ = $2^M$, \textbf{Offset} = $N$ bits, \textbf{Set Index} = $M$ bits
\subsection{Fully Associative Cache \textmd{ -- capacity miss, \underline{no} conflict miss}}
\textbf{How to id}: tag match for all the blocks in the cache.\\
A memory block can be placed in any location in the cache.\\
\textbf{Cache block size} = $2^N$ bytes, \textbf{no of cache blocks} = $2^M$\\
\textbf{Offset} = $N$ bits, \textbf{Tag} = $32 - N$ bits (block number = tag)

\subsection{Block Replacement Policy}
\begin{itemize}
\item \textbf{Least Recently Used (LRU)}: Replace the block which has not been accessed for the longest time. For temporal locality. \textbf{Problem:} hard to keep track if there are many choices.
\item \textbf{FIFO}, \textbf{Random Replacement}, \textbf{Least Frequently Used}
\end{itemize}

\section{Performance}
\subsection{Execution Time}
Avg Cycle/Instruction: \textbf{CPI} = $\frac{(\text{CPU time} \times \text{clock rate})}{\text{Instruction count}} = \frac{\text{clock cycles}}{\text{instruction count}}$\\
CPU time = ${seconds} = {instructions}\times\frac{cycles}{instruction}\times\frac{seconds}{cycle}$\\
$CPI = \sum\limits_{k=1}^{n}(CPI_k\times F_k)$ where $F_k = \frac{I_k \text{(Instruction frequency)}}{\text{Instruction count}}$

\subsubsection{Amdahl's Law (1967)}
Speedup of parallel execution is limited by the fraction of the algo that can't be parallelised
\begin{itemize}
\item $0 \leq f \leq 1$ = sequential fraction (fixed-workload performance)
\item $S_p(n) = \frac{T_{best\_seq}(n)}{f\times T_{best\_seq}(n)+\frac{1-f}{p}T_{best\_seq}(n)}$
\item Implication: manufacturers are discouraged from making large parallel computers, more research attn shifted towards developing parallelising compilers that reduces $f$
\item \textbf{Rebuttal}: in many computing problems, $f$ is not constant, dependent on problem size $n$. An effective parallel algorithm is $\lim\limits_{n\rightarrow\infty}f(n) = 0$, thus speedup $\lim\limits_{n\rightarrow\infty}S_p(n)=\frac{p}{1+(p-1)f(n)}=p$, thus Amdahl's law can be circumvented for large problem size
\end{itemize}
\subsubsection{Gustafson's Law (1988)}
\begin{itemize}
\item Main constraint is exec time, then higher computing power is used to improve accuracy/better result
\item If $f$ decreases when $n$ increases, then $S_p(n) \leq p$, $\lim\limits_{n\rightarrow\infty}S_p(n)=p$
\item Let $T(N)$ = exec time on $N$ processors, $ser(N)$ = exec time of seq portion, $par(N)$ = exec time of par portion
\item $T(N) = ser(N) + par(N) = 1$
\item $T(1) = ser(N) + N \times par(N)$
\item Speedup $ = \frac{T(1)}{T(N)} = ser(N) + N \times (1 - ser(N)) = N - (N - 1) \times ser(N)$
\end{itemize}

\end{multicols*}
\end{document}

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