tptriscv-v1.0

Architecture Version I, Release v1.0

It has passed almost all inspections, and the architecture works well.

Implemented Instruction Set

• RV32I: full
• RV32C: full
• RV32M: partially, exclude MULH, MULHSU, MULHU, DIVU, REMU.
• RV32A: not supported
• RV32F: not supported
• RV32D: not supported, but the register is ready.
• RV32Zicsr: not supported

Features

1. Implemented RV32IC
2. Real-Time Dis-Assembler is ready. (integrated into the decoder)
3. Easy debugging interface, via DBG material.
4. Configuration API is ready (unstable), via CFG material.
5. Direct memory access interface using FILT and RAM, serialization, and deserialization are possible.
6. Supports up to a maximum operating frequency of 2.04 kHz (60 FPS)
7. Unaligned(or misaligned) memory is accessible in 2-byte increments.

Next Update

For the time being, only bug fixes will be made.

Experimental behavior test v0.2

• Added DBG material, This material ends the entire process in one click, from creating instances, automatically loading program data, and generating memory dumps after they are terminated. (This material can probably be done many times.)
• Changed API for CFG material.
• Replaced some outdated code with a new Lua API.
• The code has been rewritten for LuaLS. Simple program logic errors can now be detected before execution.
• It will be officially distributed at 21:00 South Korean time (12:00 global time).