Co Pro 68000: Final touches to an initial release

Change-Id: I8953696f493addb3567976f8a6325d4049c9b025
hoglet67 · Sep 12, 2015 · 5deedba · 5deedba
1 parent 83e0529
commit 5deedba
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Showing 7 changed files with 251 additions and 242 deletions.
diff --git a/LX9Co-68000.xise b/LX9Co-68000.xise
@@ -16,7 +16,7 @@
 
   <files>
     <file xil_pn:name="src/DCM/dcm_32_16.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
     </file>
     <file xil_pn:name="src/Tube/hp_byte.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
@@ -40,13 +40,13 @@
       <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
     </file>
     <file xil_pn:name="src/Tube/tube.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
     </file>
     <file xil_pn:name="src/LX9Co_CoPro68000.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
     </file>
     <file xil_pn:name="src/ROM/tuberom_68000.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
     </file>
     <file xil_pn:name="src/SYS09/cpu09l.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
@@ -65,19 +65,19 @@
     </file>
     <file xil_pn:name="src/ICAP_config.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="68"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
     </file>
     <file xil_pn:name="src/ICAP_core.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="69"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
     </file>
     <file xil_pn:name="src/TG68/TG68_fast.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
     </file>
     <file xil_pn:name="src/TG68/TG68.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
     </file>
     <file xil_pn:name="src/LX9Co_6SLX9TQG144_U1_16bitRam.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>

diff --git a/gen_mcs.sh b/gen_mcs.sh
@@ -12,8 +12,8 @@
 # design 10xx      - 0x1f8000 - working/LX9CoPro6502fast.bit (32/16/8/4MHz)
 # design 11xx      - 0x24c000 - working/LX9CoProZ80fast.bit(36/24/12/8Mhz)
 # design 0111      - 0x2a0000 - working/LX9CoProPDP11.bit
-# design 0110      - 0x2f4000 - spare
-# design 0101      - 0x348000 - spare
+# design 0110      - 0x2f4000 - working/LX9CoProNull.bit
+# design 0101      - 0x348000 - working/LX9CoPro68000.bit
 # design ????      - 0x39c000 - spare
 
 NAME=multiboot/LX9CoProCombined_$(date +"%Y%m%d_%H%M")_$USER
@@ -31,6 +31,7 @@ promgen                                 \
 -u 24C000 working/LX9CoProZ80fast.bit   \
 -u 2A0000 working/LX9CoProPDP11.bit     \
 -u 2F4000 working/LX9CoProNull.bit      \
+-u 348000 working/LX9CoPro68000.bit     \
 -o $NAME.mcs  -p mcs -w -spi -s 8192
 
 rm -f $NAME.cfi $NAME.prm

diff --git a/ise_build_all.tcl b/ise_build_all.tcl
@@ -26,6 +26,9 @@ project close
 project open LX9Co-PDP11.xise
 process run "Generate Programming File"
 project close
+project open LX9Co-68000.xise
+process run "Generate Programming File"
+project close
 project open LX9Co-Null.xise
 process run "Generate Programming File"
 project close

diff --git a/ise_clean_all.tcl b/ise_clean_all.tcl
@@ -26,6 +26,9 @@ project close
 project open LX9Co-PDP11.xise
 project clean
 project close
+project open LX9Co-68000.xise
+project clean
+project close
 project open LX9Co-Null.xise
 project clean
 project close

diff --git a/src/ICAP_core.v b/src/ICAP_core.v
@@ -334,6 +334,7 @@ module ICAP_core
                  5'b00010: icap_din    = 16'hC000;
                  5'b00011: icap_din    = 16'h0000;
                  5'b00100: icap_din    = 16'h4000;
+                 5'b00101: icap_din    = 16'h8000;
                  5'b00111: icap_din    = 16'h0000;
                  5'b01000: icap_din    = 16'h8000;
                  5'b01001: icap_din    = 16'h8000;
@@ -369,6 +370,7 @@ module ICAP_core
                  5'b00010: icap_din    = 16'h030f;
                  5'b00011: icap_din    = 16'h0315;
                  5'b00100: icap_din    = 16'h031a;
+                 5'b00101: icap_din    = 16'h0334;
                  5'b00111: icap_din    = 16'h032a;
                  5'b01000: icap_din    = 16'h031f;
                  5'b01001: icap_din    = 16'h031f;

diff --git a/src/LX9Co_CoPro68000.vhd b/src/LX9Co_CoPro68000.vhd
@@ -87,17 +87,17 @@ begin
 -- instantiated components
 ---------------------------------------------------------------------
 
---    inst_ICAP_config : entity work.ICAP_config port map (
---        fastclk => fastclk,
---        sw_in   => sw,
---        sw_out  => open,
---        h_addr  => h_addr,
---        h_cs_b  => h_cs_b,
---        h_data  => h_data,
---        h_phi2  => h_phi2,
---        h_rdnw  => h_rdnw,
---        h_rst_b => h_rst_b 
---    );
+    inst_icap_config : entity work.icap_config port map (
+        fastclk => fastclk,
+        sw_in   => sw,
+        sw_out  => open,
+        h_addr  => h_addr,
+        h_cs_b  => h_cs_b,
+        h_data  => h_data,
+        h_phi2  => h_phi2,
+        h_rdnw  => h_rdnw,
+        h_rst_b => h_rst_b 
+    );
 
     inst_dcm_32_16 : entity work.dcm_32_16 port map (
         CLKIN_IN   => fastclk,
@@ -117,7 +117,7 @@ begin
         clkena_in  => cpu_clken,
         data_in    => cpu_din,
         IPL        => CPU_NMI_n_sync & CPU_IRQ_n_sync & CPU_NMI_n_sync,
-        dtack      => '0', -- TODO FIXME
+        dtack      => '0',
         addr       => cpu_addr,
         data_out   => cpu_dout,
         as         => cpu_as,