Fix cpu.md misinfo/typo

[AidenBeresford]

The ARM7TDMI has 37 registers. You can reference the technical manual (Section 2.6) for more information. You can also count out the registers already listed.

[AntonioND]

Is this information even relevant? I think we should just remove the count because "17 registers" doesn't really give any useful information. One of them is the program counter, another one the stack pointer, another one the link register, another one is the CPU status register. Even though the SP is only assigned by convention in ARM mode, it is assigned to r13 in Thumb mode. So basically you have r0-r12, and 4 registers that have specific purposes. Adding them all doesn't seem particularly useful.

[AidenBeresford]

Is this information even relevant? I think we should just remove the count because "17 registers" doesn't really give any useful information. One of them is the program counter, another one the stack pointer, another one the link register, another one is the CPU status register. Even though the SP is only assigned by convention in ARM mode, it is assigned to r13 in Thumb mode. So basically you have r0-r12, and 4 registers that have specific purposes. Adding them all doesn't seem particularly useful.

It should be reworked entirely because even 17 isn't technically right. It's between 17 and 18 depending on the processor mode. I would go as far as to say that the information listed isn't descriptive enough.
From my limited purview of one currently unfinished GBA emulator I think it would be more beneficial to rework this paragraph to say something along the lines of:

"The processor has a total of 37 registers, but it can only access 17 or 18 at any one point. The remaining registers are banked depending on the processor mode. The first 8 registers are the low registers (r0-r7), they are for general-use and remain the same regardless of processor mode. The next 8 registers are the high registers and can be swapped with the banked registers. Within the high registers, the first 5 (r8-r12) are for general-use. The remaining 3 represent the Stack Pointer (r13), the Link Register (r14), and the Program Counter (r15) respectively. The last 2 registers are the CPSR and SPSR. The CPSR is static and can be accessed in any processor mode, while the SPSR can be swapped with banked registers and is inaccessible by the User and System processor modes."

A little wordy but I think the minor details are important here. ARM also just has a chart you could probably use or link to.
https://developer.arm.com/documentation/ddi0210/c/Programmer-s-Model/Registers/The-ARM-state-register-set

Edit: Oh and obviously also include the stuff I forgot to mention like the 3-stage pipeline. Please rework as you see fit, this is just how I would personally find it most comprehensive.