WCH RISC V Debug Module hardware bugs

1. All bits in hartsel are implemented, instead of matching real number of harts.
2. Hart is actually running but dmstatus and haltsum0 still reads halted state, after performing a reset in halted state.
   This is possibly because halt status registers aren't resetted (together with the hart) during reset.
3. abstractauto register is writable, but the feature is not implemented.
4. ndmreset does not reset peripherals, while RISC-V spec says it should reset every part of the system.