Error compiling on gnuc < 9, definition of alias uClibc.

.gitignore

@@ -19,10 +19,12 @@
 # VIM Swap Files
 ######################
 *.swp
+*.un~
 
 # Build directory
 ######################
 build/
+generated/
 
 # Test failure outputs
 ######################

lib/utils/printf.c

@@ -99,7 +99,7 @@ STATIC void strn_print_strn(void *data, const char *str, size_t len) {
     strn_print_env->remain -= len;
 }
 
-#if defined(__GNUC__) && !defined(__clang__)
+#if defined(__GNUC__) && !defined(__clang__)  && __GNUC__ < 9
 // uClibc requires this alias to be defined, or there may be link errors
 // when linkings against it statically.
 int __GI_vsnprintf(char *str, size_t size, const char *fmt, va_list ap) __attribute__((weak, alias ("vsnprintf")));

ports/fupy/Makefile

@@ -0,0 +1,140 @@
+BUILDINC_DIRECTORY ?= .
+ifeq ($(wildcard $(BUILDINC_DIRECTORY)/generated/variables.mak),)
+define ERROR_MSG
+
+$(BUILDINC_DIRECTORY)/generated/variables.mak not found.
+
+MicroPython for LiteX requires these generated files to build. It
+is important that the files match the gateware you are using and
+are specific to each board / platform.
+
+The LiteX generated files are found in build output directory
+under "software/include/generated".
+
+To allow MicroPython to find these files, you must do one of the
+following;
+ * Set BUILDINC_DIRECTORY.
+ * Copy the files into a local generated directory.
+ * Run ./get-gateware.sh script (setting PLATFORM/TARGET value).
+
+endef
+$(error $(ERROR_MSG))
+endif # no generated/variables.mak
+include $(BUILDINC_DIRECTORY)/generated/variables.mak
+
+include ../../py/mkenv.mk
+
+# qstr definitions (must come before including py.mk)
+QSTR_DEFS = qstrdefsport.h
+
+# include py core make definitions
+include ../../py/py.mk
+
+CROSS_COMPILE ?= $(TRIPLE)-
+
+INC += -I.
+INC += -I../..
+INC += -I../../lib/mp-readline
+INC += -I$(BUILD)
+INC += -I$(BUILDINC_DIRECTORY)
+
+# Ensure assembler can also found our custom include files, for crt0
+ASFLAGS += -I$(BUILDINC_DIRECTORY)
+
+CFLAGS += $(CPUFLAGS)
+CFLAGS += $(INC) -Wall -Werror -std=gnu11 -ggdb $(COPT)
+CFLAGS += -Og -Wdouble-promotion -Wall -Werror
+
+ifneq ($(DEBUG), 1)
+CFLAGS += -DNDEBUG
+endif
+
+ifeq ($(COPY_TO_MAIN_RAM), 1)
+LDFLAGS += -nostartfiles -T litex.ld -Wl,[email protected] -Wl,--cref
+else
+LDFLAGS += -nostartfiles -T litex-flash.ld -Wl,[email protected] -Wl,--cref
+endif
+
+LDFLAGS += -L$(BUILDINC_DIRECTORY)
+LIBS = -Wl,-lc -Wl,-lm
+
+SRC_C = \
+	main.c \
+	uart.c \
+	isr.c \
+	modmachine.c \
+	modlitex.c \
+	litex_leds.c \
+	litex_switches.c \
+	lib/utils/stdout_helpers.c \
+	lib/utils/interrupt_char.c \
+	lib/utils/pyexec.c \
+	lib/libc/string0.c \
+	lib/mp-readline/readline.c
+
+# FIXME: Should use crt0 from newlib? However it seems to cause memory access
+# at 0x0
+
+ifeq ($(COPY_TO_MAIN_RAM), 1)
+CRT0_S ?= $(LIBBASE_DIRECTORY)/crt0-$(CPU).S
+CRT0_O = $(BUILD)/crt0-$(CPU)-ctr.o
+CRT0FLAGS =
+else ifeq ($(EXECUTE_IN_PLACE), 1)
+CRT0_S ?= $(LIBBASE_DIRECTORY)/crt0-$(CPU).S
+CRT0_O = $(BUILD)/crt0-$(CPU)-xip.o
+CRT0FLAGS = -DEXECUTE_IN_PLACE
+else
+$(error You need to define one of COPY_TO_MAIN_RAM or EXECUTE_IN_PLACE to 1)
+endif
+
+# CPU-specific overrides.
+ifeq ($(CPU), picorv32)
+# Extract the arch-specific flags, otherwise firmware won't link.
+LDFLAGS += $(filter -march=% -mabi=%, $(CPUFLAGS))
+# picorv32 needs a special assembly include to compile crt0.
+ASFLAGS += -I$(SOC_DIRECTORY)/software/include/base
+else ifeq ($(CPU), vexriscv)
+LDFLAGS += $(filter -march=% -mabi=%, $(CPUFLAGS))
+endif
+
+# No extra assembly files for now.
+SRC_S =
+
+OBJ =  $(CRT0_O) $(addprefix $(BUILD)/, $(SRC_S:.S=.o)) $(PY_O) $(addprefix $(BUILD)/, $(SRC_C:.c=.o))
+
+all: $(BUILD)/firmware.bin
+
+# List of sources for qstr extraction
+SRC_QSTR += $(SRC_C) $(SRC_LIB)
+
+# crt0 override for normal assembler rule- needed to distinguish
+# whether we need to assemble a crt0 that copies a data section to RAM from
+# flash, or a crt0 that assumes a bootloader does it ahead of time.
+$(CRT0_O): $(CRT0_S)
+	$(CC) -c $(ASFLAGS) $(CFLAGS) $(CRT0FLAGS) -o $@ $<
+
+$(BUILD)/_frozen_mpy.c: frozentest.mpy $(BUILD)/genhdr/qstrdefs.generated.h
+	$(ECHO) "MISC freezing bytecode"
+	$(Q)../tools/mpy-tool.py -f -q $(BUILD)/genhdr/qstrdefs.preprocessed.h -mlongint-impl=none $< > $@
+
+$(BUILD)/firmware.elf: $(OBJ)
+	$(ECHO) "LINK $@"
+	$(Q)$(CC) $(LDFLAGS) -o $@ $^ $(LIBS)
+	$(Q)$(SIZE) $@
+
+$(BUILD)/firmware.bin: $(BUILD)/firmware.elf
+	$(Q)$(OBJCOPY) -O binary $^ $(BUILD)/firmware.bin
+
+# Run emulation build on a POSIX system with suitable terminal settings
+run:
+	stty raw opost -echo
+	build/firmware.elf
+	@echo Resetting terminal...
+# This sleep is useful to spot segfaults
+	sleep 1
+	reset
+
+test: $(BUILD)/firmware.elf
+	$(Q)/bin/echo -e "print('hello world!', list(x+1 for x in range(10)), end='eol\\\\n')\\r\\n\\x04" | $(BUILD)/firmware.elf | tail -n2 | grep "^hello world! \\[1, 2, 3, 4, 5, 6, 7, 8, 9, 10\\]eol"
+
+include ../../py/mkrules.mk

ports/fupy/README.md

@@ -0,0 +1,35 @@
+# The minimal port
+
+This port is intended to be a minimal MicroPython port that actually runs.
+It can run under Linux (or similar) and on any STM32F4xx MCU (eg the pyboard).
+
+## Building and running Linux version
+
+By default the port will be built for the host machine:
+
+    $ make
+
+To run a small test script do:
+
+    $ make run
+
+## Building for an STM32 MCU
+
+The Makefile has the ability to build for a Cortex-M CPU, and by default
+includes some start-up code for an STM32F4xx MCU and also enables a UART
+for communication.  To build:
+
+    $ make CROSS=1
+
+If you previously built the Linux version, you will need to first run
+`make clean` to get rid of incompatible object files.
+
+Building will produce the build/firmware.dfu file which can be programmed
+to an MCU using:
+
+    $ make CROSS=1 deploy
+
+This version of the build will work out-of-the-box on a pyboard (and
+anything similar), and will give you a MicroPython REPL on UART1 at 9600
+baud.  Pin PA13 will also be driven high, and this turns on the red LED on
+the pyboard.

ports/fupy/csr-defs.h

@@ -0,0 +1,11 @@
+#ifndef CSR_DEFS__H
+#define CSR_DEFS__H
+
+#define CSR_MSTATUS_MIE 0x8
+
+#define CSR_IRQ_MASK 0xBC0
+#define CSR_IRQ_PENDING 0xFC0
+
+#define CSR_DCACHE_INFO 0xCC0
+
+#endif	/* CSR_DEFS__H */

ports/fupy/frozentest.py

@@ -0,0 +1,7 @@
+print('uPy')
+print('a long string that is not interned')
+print('a string that has unicode αβγ chars')
+print(b'bytes 1234\x01')
+print(123456789)
+for i in range(4):
+    print(i)

ports/fupy/get-gateware.sh

@@ -0,0 +1,27 @@
+#!/bin/bash
+
+PLATFORM="${PLATFORM:-mimasv2}"
+TARGET="${TARGET:-base}"
+CPU="${CPU:-lm32}"
+BRANCH="${BRANCH:-master}"
+
+GITHUB_URL=https://github.com/timvideos/HDMI2USB-firmware-prebuilt/
+
+# Automatically figure out the latest revision
+if [ "$REV" = "" ]; then
+	REV=$(svn ls $GITHUB_URL/trunk/archive/$BRANCH | sort | tail -n1 | sed -e's-/$--')
+	echo "Using revision $REV"
+fi
+
+# archive/master/v0.0.3-696-g2f815c1/minispartan6/base/lm32
+BASE_DIR=archive/$BRANCH/$REV/$PLATFORM/$TARGET/$CPU
+
+# Get the generated header files
+svn export --force $GITHUB_URL/trunk/$BASE_DIR/software/include/generated | grep -v "^Exported"
+
+# Get the flash file
+#svn export --force $SVN_URL/flash.bin
+
+# Get gateware and bios files (to allow image building)
+#svn export --force $SVN_URL/gateware/top.bin gateware.bin
+#svn export --force $SVN_URL/software/bios/bios.bin

ports/fupy/hw/common.h

@@ -0,0 +1,52 @@
+#ifndef __HW_COMMON_H
+#define __HW_COMMON_H
+
+#include <stdint.h>
+
+/* To overwrite CSR accessors, define extern, non-inlined versions
+ * of csr_read[bwl]() and csr_write[bwl](), and define
+ * CSR_ACCESSORS_DEFINED.
+ */
+
+#ifndef CSR_ACCESSORS_DEFINED
+#define CSR_ACCESSORS_DEFINED
+
+#ifdef __ASSEMBLER__
+#define MMPTR(x) x
+#else /* ! __ASSEMBLER__ */
+#define MMPTR(x) (*((volatile unsigned int *)(x)))
+
+static inline void csr_writeb(uint8_t value, uint32_t addr)
+{
+	*((volatile uint8_t *)addr) = value;
+}
+
+static inline uint8_t csr_readb(uint32_t addr)
+{
+	return *(volatile uint8_t *)addr;
+}
+
+static inline void csr_writew(uint16_t value, uint32_t addr)
+{
+	*((volatile uint16_t *)addr) = value;
+}
+
+static inline uint16_t csr_readw(uint32_t addr)
+{
+	return *(volatile uint16_t *)addr;
+}
+
+static inline void csr_writel(uint32_t value, uint32_t addr)
+{
+	*((volatile uint32_t *)addr) = value;
+}
+
+static inline uint32_t csr_readl(uint32_t addr)
+{
+	return *(volatile uint32_t *)addr;
+}
+#endif /* ! __ASSEMBLER__ */
+
+#endif /* ! CSR_ACCESSORS_DEFINED */
+
+#endif /* __HW_COMMON_H */

ports/fupy/hw/ethmac_mem.h

@@ -0,0 +1,11 @@
+#ifndef __HW_ETHMAC_MEM_H
+#define __HW_ETHMAC_MEM_H
+
+#include <generated/mem.h>
+
+#define ETHMAC_RX0_BASE	ETHMAC_BASE
+#define ETHMAC_RX1_BASE	(ETHMAC_BASE+0x0800)
+#define ETHMAC_TX0_BASE	(ETHMAC_BASE+0x1000)
+#define ETHMAC_TX1_BASE	(ETHMAC_BASE+0x1800)
+
+#endif

ports/fupy/hw/flags.h

@@ -0,0 +1,40 @@
+#ifndef __HW_FLAGS_H
+#define __HW_FLAGS_H
+
+#define UART_EV_TX	0x1
+#define UART_EV_RX	0x2
+
+#define DFII_CONTROL_SEL		0x01
+#define DFII_CONTROL_CKE		0x02
+#define DFII_CONTROL_ODT		0x04
+#define DFII_CONTROL_RESET_N	0x08
+
+#define DFII_COMMAND_CS		0x01
+#define DFII_COMMAND_WE		0x02
+#define DFII_COMMAND_CAS	0x04
+#define DFII_COMMAND_RAS	0x08
+#define DFII_COMMAND_WRDATA	0x10
+#define DFII_COMMAND_RDDATA	0x20
+
+#define ETHMAC_EV_SRAM_WRITER	0x1
+#define ETHMAC_EV_SRAM_READER	0x1
+
+#define CLKGEN_STATUS_BUSY		0x1
+#define CLKGEN_STATUS_PROGDONE	0x2
+#define CLKGEN_STATUS_LOCKED	0x4
+
+#define DVISAMPLER_TOO_LATE		0x1
+#define DVISAMPLER_TOO_EARLY	0x2
+
+#define DVISAMPLER_DELAY_MASTER_CAL	0x01
+#define DVISAMPLER_DELAY_MASTER_RST	0x02
+#define DVISAMPLER_DELAY_SLAVE_CAL	0x04
+#define DVISAMPLER_DELAY_SLAVE_RST	0x08
+#define DVISAMPLER_DELAY_INC		0x10
+#define DVISAMPLER_DELAY_DEC		0x20
+
+#define DVISAMPLER_SLOT_EMPTY	0
+#define DVISAMPLER_SLOT_LOADED	1
+#define DVISAMPLER_SLOT_PENDING	2
+
+#endif /* __HW_FLAGS_H */