GitHub - ericksuzart/FPGA-BlackJack: BlackJack game in verilog · GitHub

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FPGA-BlackJack

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BlackJack game in verilog

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Name		Name	Last commit message	Last commit date
FSM		FSM
Modelsim/BlackJack		Modelsim/BlackJack
Quartus/BlackJack		Quartus/BlackJack
.gitignore		.gitignore
BlackJack.pdf		BlackJack.pdf
README.md		README.md
combinations.py		combinations.py
combinations.txt		combinations.txt

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BlackJack game in verilog

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