[pull] master from sogno-platform:master #37
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adds a new data logger interface for simulation result logging. Besides the existing DataLogger, the interface is implemented by the new RealTimeDataLogger that preallocates a buffer for the results and only writes them after the simulation finished. This does not break existing code. Signed-off-by: Niklas Eiling <[email protected]>
Signed-off-by: Niklas Eiling <[email protected]>
Signed-off-by: Niklas Eiling <[email protected]>
Signed-off-by: Niklas Eiling <[email protected]>
Signed-off-by: Niklas Eiling <[email protected]>
This adds FpgaCosimulation.cpp, an example for a cosimulation with another simulator running a WSCC 9 bus and DPsim running the load connected to bus 5. This also modifies EMT::Ph3::RXLoad to allow it to represent an R-L series load rather than only a parallel load. It also adds EMT::Ph3::ControlledVoltageSource, a voltage source with EMT setpoints for feeding interface data into the DPsim simulation. Signed-off-by: Niklas Eiling <[email protected]>
Signed-off-by: Niklas Eiling <[email protected]>
Signed-off-by: Niklas Eiling <[email protected]>
…PHIL and co-simulation Signed-off-by: Niklas Eiling <[email protected]>
Signed-off-by: Niklas Eiling <[email protected]>
…ake simulation more stable Signed-off-by: Niklas Eiling <[email protected]>
…iles. Signed-off-by: Niklas Eiling <[email protected]>
Signed-off-by: Niklas Eiling <[email protected]>
Signed-off-by: Niklas Eiling <[email protected]>
Signed-off-by: Niklas Eiling <[email protected]>
…n when drawing the system topology. Signed-off-by: Niklas Eiling <[email protected]>
Signed-off-by: Niklas Eiling <[email protected]>
…faster but compilation a lot slower. Signed-off-by: Niklas Eiling <[email protected]>
Signed-off-by: Niklas Eiling <[email protected]>
Signed-off-by: Niklas Eiling <[email protected]>
Signed-off-by: Niklas Eiling <[email protected]>
Signed-off-by: Niklas Eiling <[email protected]>
The CI does not have this issue This reverts commit 0cd8c4a. Signed-off-by: Niklas Eiling <[email protected]>
Signed-off-by: Niklas Eiling <[email protected]>
…t_parameters Signed-off-by: Niklas Eiling <[email protected]>
Signed-off-by: Niklas Eiling <[email protected]>
Signed-off-by: Niklas Eiling <[email protected]>
Signed-off-by: Niklas Eiling <[email protected]>
Signed-off-by: Niklas Eiling <[email protected]>
Signed-off-by: Niklas Eiling <[email protected]>
Signed-off-by: Niklas Eiling <[email protected]>
Signed-off-by: Niklas Eiling <[email protected]>
Signed-off-by: Niklas Eiling <[email protected]>
- add a real time data logger This writes simulation results to memory and only dumps to a file when the simulation ends. It allocates a buffer that is attributes*simulation duration/time step long - so this only works for relatively short simulations. - adds `EMT::Ph3::ControlledVoltageSource` and `EMT::Ph3::ControlledCurrentSource`. The existing sources `EMT::Ph3::VoltageSource` and `EMT::Ph3::CurrentSource` only allow setting RMS voltages and derives the individual phase voltages from that. This cannot be used for PHIL or Co-Simulations where we need the set each phase voltage individually. The existing voltage source can also not be easily adapted to support both, so I created a new model (RTDS and Simulink also have a separate model for this so it makes sense). - modifies `EMT::Ph3::RXLoad` to be able to implement a series R-L load instead of only a parallel R-L load. The series load is needed for the WSCC 9 bus model. - adds `FPGACosimulation`, an example of using dpsim-villas to build a co-simulation where DPsim simulates load connected to bus 5 in a WSCC 9 bus model. - add `FPGACosim3PhInfiniteBus`, an example that implements an infinite bus to be connected with a load in another simulator. - make logging step times optional, as this slows down the simulation quite a bit when running in real time. - None of the changes should break existing code, because everything is again optional and the default behavior is the old behavior.
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