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add regs_analog_ctrl_APB #37

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add regs_analog_ctrl_APB #37

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58 changes: 58 additions & 0 deletions regs_analog_ctrl_APB/base.sdc
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## CLOCK CONSTRAINTS
create_clock [get_ports $::env(CLOCK_PORT)] -name $::env(CLOCK_PORT) -period 15
set_propagated_clock [get_clocks $::env(CLOCK_PORT)]
# set_clock_transition 1.5 [get_clocks $::env(CLOCK_PORT)]
set_driving_cell -lib_cell sky130_fd_sc_hd__clkbuf_4 -pin {X} [get_ports $::env(CLOCK_PORT)]
set_clock_uncertainty 0.1 [get_clocks $::env(CLOCK_PORT)]

## INPUT DELAY
set_input_transition 0.5 [all_inputs]
set_input_delay 4.8 -clock [get_clocks $::env(CLOCK_PORT)] [all_inputs]
set_input_delay -min 3.2 -clock [get_clocks $::env(CLOCK_PORT)] [get_ports PADDR*]

set_input_delay 0 -clock [get_clocks $::env(CLOCK_PORT)] [get_ports PCLK]



## OUTPUT DELAY
set_output_delay 4.8 -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]

#Menna to avoid infeasable path from and to the following two points
set_input_delay 4.8 -clock [get_clocks $::env(CLOCK_PORT)] [get_ports PADDR*]
set_input_delay -min 3.2 -clock [get_clocks $::env(CLOCK_PORT)] [get_ports PADDR*]
set_input_delay 4.8 -clock [get_clocks $::env(CLOCK_PORT)] [get_ports brownout_timeout*]
set_input_delay 4.8 -clock [get_clocks $::env(CLOCK_PORT)] [get_ports vdda1_pwr_good*]
set_input_delay 4.8 -clock [get_clocks $::env(CLOCK_PORT)] [get_ports comp_out*]
set_input_delay 4.8 -clock [get_clocks $::env(CLOCK_PORT)] [get_ports vccd2_pwr_good*]

set_input_delay 4.8 -clock [get_clocks $::env(CLOCK_PORT)] [get_ports vccd1_pwr_good*]
set_input_delay 4.8 -clock [get_clocks $::env(CLOCK_PORT)] [get_ports brownout_vunder*]
set_input_delay 4.8 -clock [get_clocks $::env(CLOCK_PORT)] [get_ports vdda2_pwr_good*]
set_input_delay 4.8 -clock [get_clocks $::env(CLOCK_PORT)] [get_ports ulpcomp_out*]
set_input_delay 4.8 -clock [get_clocks $::env(CLOCK_PORT)] [get_ports overvoltage_out*]
set_input_delay 4.8 -clock [get_clocks $::env(CLOCK_PORT)] [get_ports brownout_filt*]
set_input_delay 4.8 -clock [get_clocks $::env(CLOCK_PORT)] [get_ports brownout_unfilt*]
set_input_delay 4.8 -clock [get_clocks $::env(CLOCK_PORT)] [get_ports vccd2_pwr_good*]


set_output_delay 4.5 -clock [get_clocks $::env(CLOCK_PORT)] [get_ports PRDATA*]



## CAP LOAD
set cap_load 0.075
puts "\[INFO\]: Setting load to: $cap_load"
set_load $cap_load [all_outputs]

## MAX TRANS
set_max_transition 1 [current_design]

## DERATES
puts "\[INFO\]: Setting timing derate to: [expr {5 * 100}] %"
set_timing_derate -early 0.95
set_timing_derate -late 1.05

#Menna Oct30
# Maximum fanout
set_max_fanout $::env(MAX_FANOUT_CONSTRAINT) [current_design]
puts "\[INFO\]: Setting maximum fanout to: $::env(MAX_FANOUT_CONSTRAINT)"
51 changes: 51 additions & 0 deletions regs_analog_ctrl_APB/config.yaml
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{
"DESIGN_NAME": "regs_analog_ctrl_APB",
"FP_PDN_SKIPTRIM": true,
"DESIGN_IS_CORE": false,
"VERILOG_FILES": [
"dir::regs_analog_ctrl_APB.v",
"dir::regs_analog_ctrl.v"
],
"PNR_SDC_FILE":"dir::base.sdc",
"CLOCK_PORT":"PCLK",
"SIGNOFF_SDC_FILE":"dir::signoff.sdc",
"ERROR_ON_SYNTH_CHECKS": false,
"DRT_THREADS": 16,
"FP_SIZING": "absolute",
"DIE_AREA": [0, 0, 1605, 105],
"CORE_AREA": [5, 5, 1600, 100],
"FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
"PL_TARGET_DENSITY_PCT": 25,

"GPL_CELL_PADDING": 3,
"MAX_FANOUT_CONSTRAINT": 16,


"PL_WIRE_LENGTH_COEF": 0.1,
"PL_ROUTABILITY_DRIVEN": true,
"MAGIC_DEF_LABELS": false,
"GRT_ADJUSTMENT": 0.05,
"RT_MAX_LAYER": "met3",
"VDD_NETS": [
"vccd0"
],
"GND_NETS": [
"vssd0"
],
"GRT_ALLOW_CONGESTION": true,
"DIODE_ON_PORTS": "both",
"RUN_HEURISTIC_DIODE_INSERTION": true,
"GRT_REPAIR_ANTENNAS": true,
"HEURISTIC_ANTENNA_THRESHOLD": 200,
"TOP_MARGIN_MULT": 2,
"BOTTOM_MARGIN_MULT": 2,
"PDN_OBSTRUCTIONS": [
[met4,1090,0,1180,105]
],
"ROUTING_OBSTRUCTIONS": [
[met4,1090,0,1180,105]
],
"DEFAULT_CORNER": "max_ss_100C_1v60",
"DESIGN_REPAIR_MAX_WIRE_LENGTH": 1200,
"PL_KEEP_RESIZE_BELOW_OVERFLOW": 0
}
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