try rtl updates to fix the bugs

efabless · Feb 20, 2024 · a860469 · a860469
1 parent f42b4ec
commit a860469
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Showing 2 changed files with 13 additions and 6 deletions.
diff --git a/hdl/rtl/EF_UART.v b/hdl/rtl/EF_UART.v
@@ -40,6 +40,7 @@
 `timescale			1ns/1ps
 `default_nettype		none
 
+`include "aucohl_lib.v"
 
 module EF_UART #(parameter  MDW = 9,        // Max data size/width
                                 FAW = 4,        // FIFO Address width; Depth=2^AW
@@ -199,8 +200,8 @@ module EF_UART #(parameter  MDW = 9,        // Max data size/width
                 samples_count <= samples_count + 1'b1;
     end
 
-    assign tx_level_below = (tx_level < txfifotr);
-    assign rx_level_above = (rx_level > rxfifotr);
+    assign tx_level_below = (tx_level < txfifotr & ~tx_full);
+    assign rx_level_above = (rx_level > rxfifotr | rx_full);
     assign overrun_flag = rx_full & rx_done;
     assign timeout_flag = (bits_count == timeout_bits);
 
@@ -266,7 +267,7 @@ module UART_RX #(parameter NUM_SAMPLES = 16, MDW = 8)(
     reg [3:0]   b_reg;            //baud-rate/over sampling counter
     reg [3:0]   b_next;
     reg [3:0]   count_reg;        //data-bit counter
-    reg [2:0]   count_next;
+    reg [3:0]   count_next;
     reg [8:0]   data_reg;         //data register
     reg [8:0]   data_next;
     reg         p_error_reg;
@@ -308,6 +309,7 @@ module UART_RX #(parameter NUM_SAMPLES = 16, MDW = 8)(
         data_next = data_reg;
         rx_done = 1'b0;
         p_error_next = 1'b0;
+        f_error_next = 1'b0;
 
         case(current_state)
             idle_st:
@@ -441,8 +443,8 @@ module UART_TX #(parameter NUM_SAMPLES = 16, MDW = 8)(
     reg [2:0]   next_state;
     reg [3:0]   b_reg;          // baud tick counter
     reg [3:0]   b_next;
-    reg [2:0]   count_reg;      // data bit counter
-    reg [2:0]   count_next;
+    reg [3:0]   count_reg;      // data bit counter
+    reg [3:0]   count_next;
     reg [8:0]   data_reg;       // data register
     reg [8:0]   data_next;
     reg         tx_reg;         // output data reg

diff --git a/hdl/rtl/bus_wrappers/EF_UART_APB.v b/hdl/rtl/bus_wrappers/EF_UART_APB.v
@@ -243,7 +243,12 @@ module EF_UART_APB #(
 	assign PREADY = 1'b1;
 
 	assign	RXDATA_WIRE = rdata;
-	assign	rd = (apb_re & (PADDR[`APB_AW-1:0] == RXDATA_REG_OFFSET));
+	reg apb_re_delayed;
+	always @( posedge PCLK ) begin
+		apb_re_delayed <= apb_re;
+
+	end
+	assign	rd = (apb_re_delayed & (PADDR[`APB_AW-1:0] == RXDATA_REG_OFFSET));
 	assign	wdata = PWDATA;
 	assign	wr = (apb_we & (PADDR[`APB_AW-1:0] == TXDATA_REG_OFFSET));
 endmodule