update README.md

README.md

@@ -189,7 +189,7 @@ TX_FIFO Flush Register
 
 ### Interrupt Flags
 
-The wrapped IP provides four registers to deal with interrupts: IM, RIS, MIS and IC. These registers exist for all wrapper types generated by the [BusWrap](https://github.com/efabless/BusWrap/tree/main) `bus_wrap.py` utility. 
+The wrapped IP provides four registers to deal with interrupts: IM, RIS, MIS and IC. These registers exist for all wrapper types generated.
 
 Each register has a group of bits for the interrupt sources/flags.
 - `IM` [offset: 0xff00]: is used to enable/disable interrupt sources.
@@ -277,6 +277,7 @@ VERILOG_DEFINES:
 |overrun_flag|output|1|Overrun flag|
 |timeout_flag|output|1|Timeout flag|
 ## F/W Usage Guidelines:
+For details on the firmware APIs, see the [Firmware API Documentation](fw/README.md).
 1. Set the prescaler according to the required transmission and receiving baud rate where:  $Baud\ rate = Bus\ Clock\ Freq/((Prescaler+1)\times16)$. Setting the prescaler is done through writing to ``PR`` register
 2. Configure the frame format by :
   * Choosing the number of data bits which could vary from 5 to 9. This is done by setting the ```wlen``` field in the ```CFG``` register