update docs and fw license

README.md

@@ -225,7 +225,7 @@ The following are the bit definitions for the interrupt registers:
 |8|OR|1|Overrun; data has been received but the RX FIFO is full.|
 |9|RTO|1|Receiver Timeout; no data has been received for the time of a specified number of bits.|
 ### Clock Gating
-The IP includes a clock gating feature that allows selective activation and deactivation of the clock using the ``GCLK`` register. This capability is implemented through the ``ef_util_gating_cell`` module, which is part of the the common modules library, [ef_util_lib.v](https://github.com/efabless/EF_IP_UTIL/blob/main/hdl/ef_util_lib.v). By default, the clock gating is disabled. To enable behavioral implmentation clock gating, only for simulation purposes, you should define the ``CLKG_GENERIC`` macro. Alternatively, define the ``CLKG_SKY130_HD`` macro if you wish to use the SKY130 HD library clock gating cell, ``sky130_fd_sc_hd__dlclkp_4``.
+The IP includes a clock gating feature that allows selective activation and deactivation of the clock using the ``GCLK`` register. This capability is implemented through the ``ef_util_gating_cell`` module, which is part of the common modules library, [ef_util_lib.v](https://github.com/efabless/EF_IP_UTIL/blob/main/hdl/ef_util_lib.v). By default, the clock gating is disabled. To enable behavioral implmentation clock gating, only for simulation purposes, you should define the ``CLKG_GENERIC`` macro. Alternatively, define the ``CLKG_SKY130_HD`` macro if you wish to use the SKY130 HD library clock gating cell, ``sky130_fd_sc_hd__dlclkp_4``.
 
 **Note:** If you choose the [OpenLane2](https://github.com/efabless/openlane2) flow for implementation and would like to enable the clock gating feature, you need to add ``CLKG_SKY130_HD`` macro to the ``VERILOG_DEFINES`` configuration variable. Update OpenLane2 YAML configuration file as follows: 
 ```
@@ -289,13 +289,13 @@ VERILOG_DEFINES:
 Firmware drivers for EF_UART can be found in the [fw](https://github.com/efabless/EF_UART/tree/main/fw) directory. EF_UART driver documentation  is available [here](https://github.com/efabless/EF_UART/blob/main/fw/README.md).
 You can also find an example C application using the EF_UART drivers [here]().
 ## Installation:
-You can install the IP either by cloning this repository or by using [IPM](https://github.com/efabless/IPM). 
+You can install the IP either by cloning this repository or by using [IPM](https://github.com/efabless/IPM).
 ##### 1. Using [IPM](https://github.com/efabless/IPM):
 - [Optional] If you do not have IPM installed, follow the installation guide [here](https://github.com/efabless/IPM/blob/main/README.md)
 - After installing IPM, execute the following command ```ipm install EF_UART```.
 > **Note:** This method is recommended as it automatically installs [EF_IP_UTIL](https://github.com/efabless/EF_IP_UTIL.git) as a dependency.
 ##### 2. Cloning this repo: 
-- Clone [EF_IP_UTIL](https://github.com/efabless/EF_IP_UTIL.git) repository, which includes the required modules from the common.
+- Clone [EF_IP_UTIL](https://github.com/efabless/EF_IP_UTIL.git) repository, which includes the required modules from the common modules library, [ef_util_lib.v](https://github.com/efabless/EF_IP_UTIL/blob/main/hdl/ef_util_lib.v).
 ```git clone https://github.com/efabless/EF_IP_UTIL.git```
 - Clone the IP repository
 ```git clone https://github.com/efabless/EF_UART.git```

fw/EF_UART_regs.h

@@ -1,7 +1,7 @@
 /*
 	Copyright 2024 Efabless Corp.
 
-	Author: Mohamed Shalan (mshalan@efabless.com)
+	Author: Efabless Corp. (ip_admin@efabless.com)
 
 	Licensed under the Apache License, Version 2.0 (the "License");
 	you may not use this file except in compliance with the License.

verify/README.md

@@ -3,29 +3,16 @@ In IP directory run:
  ```shell
  cd verify/uvm-python/
  ```
- ##### To run testbench for design with APB 
+ ##### To run testbench for design with certain bus type 
  To run all tests:
  ```shell
- make run_all_tests BUS_TYPE=APB
+ make run_all_tests BUS_TYPE=<bus_type>
  ```
  To run a certain test:
  ```shell
- make run_<test_name> BUS_TYPE=APB
+ make run_<test_name> BUS_TYPE=<bus_type>
  ```
  To run all tests with a tag: 
  ```shell
- make run_all_tests TAG=<new_tag> BUS_TYPE=APB
+ make run_all_tests TAG=<new_tag> BUS_TYPE=<bus_type>
  ```
- ##### To run testbench for design with APB
- To run all tests:
- ```shell
- make run_all_tests BUS_TYPE=AHB
- ```
- To run a certain test:
- ```shell
- make run_<test_name> BUS_TYPE=AHB
- ```
- To run all tests with a tag: 
- ```shell
- make run_all_tests TAG=<new_tag> BUS_TYPE=AHB
-```