Merge pull request #3 from efabless/guard_clock_gate_cell

Guard clock gating cell
efabless · Dec 15, 2024 · fb43a6d · fb43a6d
2 parents a5329e1 + f48ebb2
commit fb43a6d
Showing 1 changed file with 13 additions and 16 deletions.
diff --git a/scripts/bus_wrap.py b/scripts/bus_wrap.py
@@ -196,22 +196,19 @@ def print_wires(bus_type):
 
     # print the clock gating cell
     clkgatecell = f"""
-        reg [0:0] GCLK_REG;
-        wire clk_g;
-        wire clk_gated_en = GCLK_REG[0];
-
-    (* keep *) sky130_fd_sc_hd__dlclkp_4 clk_gate(
-    `ifdef USE_POWER_PINS 
-        .VPWR(VPWR), 
-        .VGND(VGND), 
-        .VNB(VGND),
-		.VPB(VPWR),
-    `endif 
-        .GCLK(clk_g), 
-        .GATE(clk_gated_en), 
-        .CLK({clk_net})
-        );
-        """
+    reg [0:0] GCLK_REG;
+    wire clk_g;
+    wire clk_gated_en = GCLK_REG[0];
+    ef_gating_cell clk_gate_cell(
+        `ifdef USE_POWER_PINS 
+        .vpwr(VPWR),
+        .vgnd(VGND),
+        `endif // USE_POWER_PINS
+        .clk({clk_net}),
+        .clk_en(clk_gated_en),
+        .clk_o(clk_g)
+    );
+    """
     print(clkgatecell)
     # Print clock wire declaration
     print(f"\twire\t\t{IP['clock']['name']} = clk_g;") #{clk_net};")