Add pattern matching for SVE intrinsics that operate on mask operands #114438

snickolls-arm · 2025-04-09T13:43:28Z

Introduces fgMorphTryUseAllMaskVariant for ARM64 that looks for various named intrinsics that have operands that look 'mask-like'. E.g. source operands originating from Sve.CreateTrueMask* may be recognized as masks, causing the JIT to prefer to use the predicated version of the instruction as codegen for the intrinsic. It will also inspect ConditionalSelect intrinsic nodes to match instructions with governing predicates. The transform runs during morph.

It's possible to emit the following instructions after this patch:

* ZIP{1,2} <Pd>.<T>, <Pn>.<T>, <Pm>.<T> (Sve.ZipLow, Sve.ZipHigh)
* UZP{1,2} <Pd>.<T>, <Pn>.<T>, <Pm>.<T> (Sve.UnzipEven, Sve.UnzipOdd)
* TRN{1,2} <Pd>.<T>, <Pn>.<T>, <Pm>.<T> (Sve.TransposeEven, Sve.TransposeOdd)
* REV <Pd>.<T>, <Pn>.<T>                (Sve.ReverseElement)
* AND <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B    (Sve.And)
* BIC <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B    (Sve.BitwiseClear)
* EOR <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B    (Sve.Xor)
* ORR <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B    (Sve.Or)
* SEL <Pd>.B, <Pg>, <Pn>.B, <Pm>.B      (Sve.ConditionalSelect)

Contributes towards #101970

snickolls-arm · 2025-04-09T13:43:46Z

@a74nh @kunalspathak

a74nh · 2025-04-09T15:10:46Z

It'd be nice to add some disasm tests here. But I don't think we currently can for SVE (we couldn't back in #109286 from what I remember).

AIUI, the problem is the ARM64-FULL-LINE command has to be valid where ever it's run, and we can't just work around it by putting an if(SVE) check around it.

Has that issue gone away now we have cobalt in the CI?

Alternatively, could we add ARM64-SVE-FULL-LINE to the disasmcheck infrastructure?

a74nh · 2025-04-09T15:15:59Z

src/coreclr/jit/hwintrinsicarm64.cpp

+//
+GenTree* Compiler::gtNewSimdAllFalseMaskNode(unsigned simdSize)
+{
+    return gtNewSimdHWIntrinsicNode(TYP_MASK, NI_Sve_CreateFalseMaskByte, CORINFO_TYPE_BYTE, simdSize);


I'm not sure on this line.

It should be switch(type) case byte: NI_Sve_CreateFalseMaskByte; case Int32: NI_Sve_CreateFalseMaskInt32 etc etc to keep to the hwintrinsiclistarm64sve.h interface.

However, regardless of which is used, it'll still produce the same pfalse instruction.

Alternatively, add a NI_Sve_CreateFalseMaskAll similar to NI_Sve_CreateTrueMaskAll which can take any type. But that require support adding to a few additional files.

kunalspathak · 2025-04-10T15:09:09Z

Seems some test failure

Beginning scenario: ConditionalSelect_FalseOp_all - operation in FalseValue

Assert failure(PID 9260 [0x0000242c], Thread: 8020 [0x1f54]): Assertion failed 'ins != INS_invalid' in 'JIT.HardwareIntrinsics.Arm._Sve.SimpleBinaryOpTest__Sve_AbsoluteCompareGreaterThan_float:ConditionalSelect_ZeroOp():this' during 'Generate code' (IL size 231; hash 0xca76bdfb; FullOpts)

    File: D:\a\_work\1\s\src\coreclr\jit\hwintrinsiccodegenarm64.cpp:363
    Image: C:\h\w\A54C0924\p\corerun.exe

Introduces `fgMorphTryUseAllMaskVariant` for ARM64 that looks for various named intrinsics that have operands that look 'mask-like'. E.g. source operands originating from Sve.CreateTrueMask* may be recognized as masks, causing the JIT to prefer to use the predicated version of the instruction as codegen for the intrinsic. It will also inspect ConditionalSelect intrinsic nodes to match instructions with governing predicates. The transform runs during morph. It's possible to emit the following instructions after this patch: * ZIP{1,2} <Pd>.<T>, <Pn>.<T>, <Pm>.<T> (Sve.ZipLow, Sve.ZipHigh) * UZP{1,2} <Pd>.<T>, <Pn>.<T>, <Pm>.<T> (Sve.UnzipEven, Sve.UnzipOdd) * TRN{1,2} <Pd>.<T>, <Pn>.<T>, <Pm>.<T> (Sve.TransposeEven, Sve.TransposeOdd) * REV <Pd>.<T>, <Pn>.<T> (Sve.ReverseElement) * AND <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B (Sve.And) * BIC <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B (Sve.BitwiseClear) * EOR <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B (Sve.Xor) * ORR <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B (Sve.Or) * SEL <Pd>.B, <Pg>, <Pn>.B, <Pm>.B (Sve.ConditionalSelect) Contributes towards dotnet#101970

snickolls-arm · 2025-04-23T15:17:07Z

@kunalspathak I have fixed the test and some other build issues, this should be ready for review now.

kunalspathak

Added some questions/suggestion

kunalspathak · 2025-04-23T19:53:34Z

src/coreclr/jit/morpharm64.cpp

+{
+    switch (GetHWIntrinsicId())
+    {
+        // ZIP1 <Pd>.<T>, <Pn>.<T>, <Pm>.<T>


wondering if we should add a HW_Flag_AllMaskVariant for this?

I didn't want to use flag space as this list is unlikely to grow, these were the only instructions I could find that follow this pattern across all versions of SVE. But it might make it easier to apply this transform to other intrinsics in future if we find other patterns work too.

kunalspathak · 2025-04-23T19:59:36Z

src/coreclr/jit/morpharm64.cpp

+//
+GenTree* Compiler::fgMorphTryUseAllMaskVariant(GenTreeHWIntrinsic* node)
+{
+    if (node->HasAllMaskVariant() && canMorphAllVectorOperandsToMasks(node))


It makes sense to have node->HasAllMaskVariant() inside canMorphAllVectorOperandsToMasks() itself. That way for conditional select's left operand too, you can (and should) exercise it.

I agree with this change if all of these intrinsics have HasAllMaskVariant() == true, but I don't think this works, see my comment below.

If #114438 (comment) works, then consider tagging them with HW_Flag_AllMaskVariant, move the HasAllMaskVariant() inside canMorphAllVectorOperandsToMasks. Having HW_Flag_AllMaskVariant in table helps in easy discoverability of various flags in one place.

kunalspathak · 2025-04-23T20:02:37Z

src/coreclr/jit/morpharm64.cpp

+                    // BIC <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
+                    // EOR <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
+                    // ORR <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
+                    case NI_Sve_And:


i think these too should be marked as HW_Flag_AllMaskVariant and looked for in HasAllMaskVariant() itself.

I tried grouping these intrinsics with the others initially but it doesn't work because these ones should only be considered in relation to a ConditionalSelect. Grouping them with the others causes a transformation to run when a ConditionalSelect is not present, which wouldn't be correct for these instructions because they require the mask parameter for the governing predicate.

We wrap the IR nodes that has embedded mask semantics like And inside a ConditionalSelect during lowering, which runs way after the morphing phase where you are doing this optimization. See if (HWIntrinsicInfo::IsEmbeddedMaskedOperation(intrinsicId)) in LowerHWIntrinsic(). Until then, they continue to hold Vector operands. If you do the transformation here for IR nodes that has And(mask, mask), it shouldn't prohibit us from wrapping it in ConditionalSelect in lowering.

Currently it's marked HW_Flag_OptionalEmbeddedMaskedOperation, so I think this wrapping isn't occurring for this intrinsic? When I try to implement it like this, it changes all the operands to masks and then tries to emit AND <Zd>.D, <Zn>.D, <Zm>.D and runs into this assert because the register types are wrong:

runtime/src/coreclr/jit/emitarm64sve.cpp

Line 2912 in c5922a1

assert(isVectorRegister(reg3)); // ddddd

The mask variant of this intrinsic has an embedded mask, but it's required for this instruction instead of optional, so there would also need to be some handling of this edge case in codegen to make sure it definitely wraps the mask variant in ConditionalSelect. It feels like there should be a separate set of flags for when the intrinsic is TYP_MASK or TYP_SIMD. E.g. HW_Flag_MaskVariant(Optional)EmbeddedMaskOperation, etc.

I think we should have a separate intrinsics And_Predicates (and likewise for other APIs that have predicates variant). They are added in the section "Special intrinsics that are generated during importing or lowering". And_Predicates should have HW_Flag_EmbeddedMaskedOperation. We can have flag HW_Flag_AllMaskVariant on SVE_And intrinsics, to detect it in morph if this can be transformed into And_Predicates variant.

We come here in the morph and see And(Vector, Vector). If operands are mask, we can transform the node into And_Predicates(Mask, Mask). During lowering, we can then transform it into CndSel(AllTrue, And_Predicates(Mask, Mask), Zero) and codegen will handle generating the predicated version of And (predicates).

This sounds much better than what I was thinking, I'll try and implement this.

I've pushed this implementation, it seems simpler. N.B. we've run out of flag space now as I've taken the last bit for HW_Flag_HasMaskVariant. We might need to think about expanding the flag space for SVE2.

I've pushed this implementation, it seems simpler. N.B. we've run out of flag space now as I've taken the last bit for HW_Flag_HasMaskVariant. We might need to think about expanding the flag space for SVE2.

Added #115474 to track this

kunalspathak · 2025-04-23T20:49:38Z

src/coreclr/jit/hwintrinsicarm64.cpp

+// Return Value:
+//    The mask
+//
+GenTree* Compiler::gtNewSimdAllFalseMaskNode(unsigned simdSize)


Suggested change

GenTree* Compiler::gtNewSimdAllFalseMaskNode(unsigned simdSize)

GenTree* Compiler::gtNewSimdFalseMaskByteNode(unsigned simdSize)

kunalspathak · 2025-04-23T20:53:52Z

src/coreclr/jit/morph.cpp

@@ -9218,6 +9218,15 @@ GenTree* Compiler::fgOptimizeHWIntrinsic(GenTreeHWIntrinsic* node)
        }
    }

+#ifdef TARGET_ARM64
+    optimizedTree = fgMorphTryUseAllMaskVariant(node);
+    if (optimizedTree != nullptr)


Having it here might be preventing the node from getting further transformations/optimizations. Should this be done towards the end of this method?

This seems fine, I've moved it later in the method.

snickolls-arm · 2025-05-12T08:41:20Z

These latest failures aren't related to this patch if I'm not mistaken. Some build and test failures on other platforms.

kunalspathak · 2025-05-13T22:07:34Z

/azp run runtime-coreclr superpmi-diffs

azure-pipelines · 2025-05-13T22:07:41Z

Azure Pipelines will not run the associated pipelines, because the pull request was updated after the run command was issued. Review the pull request again and issue a new run command.

…-variants

kunalspathak · 2025-05-13T22:19:47Z

src/coreclr/jit/hwintrinsic.h

+        return (flags & HW_Flag_HasAllMaskVariant) != 0;
+    }
+
+    static NamedIntrinsic GetMaskVariant(NamedIntrinsic id)


i know lot of methods in this file don't have method summary, but we try to add them for newly added methods. So please add a line or 2 for them.

kunalspathak · 2025-05-13T22:22:14Z

can you share the code generated for some of the test cases you have added?

snickolls-arm · 2025-05-14T09:11:02Z

can you share the code generated for some of the test cases you have added?

For example:

        public static unsafe void Main()
        {
            System.Console.WriteLine(
                Sve.ZipHigh(Sve.CreateTrueMaskInt16(), Sve.CreateFalseMaskInt16())
            );
        }

Previously generated:

...
IN0005: 000018      ptrue   p0.h
IN0006: 00001C      mov     z16.h, p0/z, #1
IN0007: 000020      pfalse  p0.b
IN0008: 000024      mov     z17.h, p0/z, #1
IN0009: 000028      zip2    z16.h, z16.h, z17.h
...

and now generates:

...
IN0005: 000018      ptrue   p0.h
IN0006: 00001C      pfalse  p1.b
IN0007: 000020      zip2    p0.h, p0.h, p1.h
IN0008: 000024      mov     z16.h, p0/z, #1
...

So we avoid the unnecessary conversions on the operands (the conversion of the result is still required as the vector is printed afterwards).

kunalspathak · 2025-05-14T15:46:00Z

src/coreclr/jit/hwintrinsic.h

    static bool HasAllMaskVariant(NamedIntrinsic id)
    {
        const HWIntrinsicFlag flags = lookupFlags(id);
        return (flags & HW_Flag_HasAllMaskVariant) != 0;
    }

+    // GetMaskVariant: Given an intrinsic that has a variant that operates on mask types, return the ID of
+    //                 this variant intrinsic. Call HasAllMaskVariant before using this function, as it will


may be in a follow-up PR, add assert(HasAllMaskVariant(id));

actually, there is a build failure, so can you fix this as well along with fixing the build error?

/__w/1/s/src/coreclr/jit/morpharm64.cpp:99:37: error: comparison of integer expressions of different signedness: ‘size_t’ {aka ‘long unsigned int’} and ‘int’ [-Werror=sign-compare] 99 | if (node->GetOperandCount() == numArgs) | ~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~

a74nh · 2025-05-15T11:20:36Z

src/coreclr/jit/morph.cpp

@@ -9679,6 +9679,15 @@ GenTree* Compiler::fgOptimizeHWIntrinsic(GenTreeHWIntrinsic* node)
        }
    }

+#ifdef TARGET_ARM64


Starting on line 9364 is there is some code for doing something very similar to this PR.

It's all wrapped in

if (GenTreeHWIntrinsic::OperIsBitwiseHWIntrinsic(oper))

And then does nothing on Arm64 because maskIntrinsicId is only set on TARGET_XARCH.

This PR's fgMorphTryUseAllMaskVariant() is effectively doing the Arm64 version. It doesn't fit into the existing code because Arm64 has more than just bitwise operations that have all mask variants (eg Zip).

Curiously, OperIsBitwiseHWIntrinsic() is only ever used by XARCH.

At a minimum, all the existing code should be put into an X64 version of fgMorphTryUseAllMaskVariant() and then call that at line 9364 for Arm64 and X64 instead of having it at the end of the function.

Better I think would be to just fill in the #elif defined(TARGET_ARM64) part and ensure the rest of that section works for Arm64. I'm not sure if it would or if it's incompatible.

Even better would be to also replace OperIsBitwiseHWIntrinsic() with:

static bool HasAllMaskVariant(NamedIntrinsic id) { #if defined(TARGET_XARCH) return (oper == GT_AND) || (oper == GT_AND_NOT) || (oper == GT_NOT) || (oper == GT_OR) || (oper == GT_OR_NOT) || (oper == GT_XOR) || (oper == GT_XOR_NOT); #else defined(TARGET_ARM64) const HWIntrinsicFlag flags = lookupFlags(id); return (flags & HW_Flag_HasAllMaskVariant) != 0; #endif }

I've implemented this by moving both XARCH and ARM64 into another function that has two conditionally compiled bodies. It should be clearer now which part of the code is trying to optimize for masked intrinsics, for both architectures.

kunalspathak · 2025-05-16T16:25:41Z

src/coreclr/jit/morpharm64.cpp

+// canMorphVectorOperandToMask: Can this vector operand be converted to a
+//                              node with type TYP_MASK easily?
+//
+bool Compiler::canMorphVectorOperandToMask(GenTree* node)


just one suggestion would be to have it in morph.cpp itself instead of creating new file. We have lot of xarch and arm64 code scattered in morph.cpp, and if we truly want morpharm64.cpp, we should move that too (someday)

kunalspathak · 2025-05-16T18:21:39Z

also, looks like there was some bug introduced in recent refactoring because of which the tests are failing. PTAL

snickolls-arm · 2025-05-19T10:19:19Z

also, looks like there was some bug introduced in recent refactoring because of which the tests are failing. PTAL

I haven't been able to reproduce this test failure in my x64 environment, is there a way I can see the exact environment of this run? I'm probably missing some stress configuration

kunalspathak · 2025-05-19T18:37:20Z

also, looks like there was some bug introduced in recent refactoring because of which the tests are failing. PTAL

I haven't been able to reproduce this test failure in my x64 environment, is there a way I can see the exact environment of this run? I'm probably missing some stress configuration

yeah, that could be because it needs AVX-512 support. I have fixed the problem, it was minor refactoring related.

kunalspathak · 2025-05-20T16:46:23Z

Build failure is from #115767.

kunalspathak

LGTM

kunalspathak · 2025-05-20T16:47:21Z

/ba-g known build failure

…#114438) * Add pattern matching for SVE intrinsics that operate on mask operands Introduces `fgMorphTryUseAllMaskVariant` for ARM64 that looks for various named intrinsics that have operands that look 'mask-like'. E.g. source operands originating from Sve.CreateTrueMask* may be recognized as masks, causing the JIT to prefer to use the predicated version of the instruction as codegen for the intrinsic. It will also inspect ConditionalSelect intrinsic nodes to match instructions with governing predicates. The transform runs during morph. It's possible to emit the following instructions after this patch: * ZIP{1,2} <Pd>.<T>, <Pn>.<T>, <Pm>.<T> (Sve.ZipLow, Sve.ZipHigh) * UZP{1,2} <Pd>.<T>, <Pn>.<T>, <Pm>.<T> (Sve.UnzipEven, Sve.UnzipOdd) * TRN{1,2} <Pd>.<T>, <Pn>.<T>, <Pm>.<T> (Sve.TransposeEven, Sve.TransposeOdd) * REV <Pd>.<T>, <Pn>.<T> (Sve.ReverseElement) * AND <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B (Sve.And) * BIC <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B (Sve.BitwiseClear) * EOR <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B (Sve.Xor) * ORR <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B (Sve.Or) * SEL <Pd>.B, <Pg>, <Pn>.B, <Pm>.B (Sve.ConditionalSelect) Contributes towards #101970 * Fix test failure and add FileCheck tests * Don't run tests on OSX * Don't run tests for Mono * Move the transform later in fgOptimizeHWIntrinsic * Rename gtNewSimdAllFalseMaskNode * Re-design using HW_Flag_AllMaskVariant * Add missing function documentation in hwintrinsic.h * Fix integer comparison and add assertion * Refactor to follow similar path to XARCH * fix the refactoring * jit formatting * Move code into morph.cpp --------- Co-authored-by: Kunal Pathak <[email protected]>

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[linux-x64] [mono-aot] Test Runtime_101731.TestConvertToInt64NativeSingle(3.4028235E+38) returns exit code 22 #112557

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Fix test failure and add FileCheck tests

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Move the transform later in fgOptimizeHWIntrinsic

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Re-design using HW_Flag_AllMaskVariant

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HWIntrinsicFlag has run out of space #115474

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Merge remote-tracking branch 'origin/main' into sve-use-all-predicate…

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Arm64/Sve: Mirror some of the morph optimizations from AVX512 #101933

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Refactor to follow similar path to XARCH

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fix the refactoring

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ARM64-SVE: Use predicate versions of instructions #101970

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ARM64 SVE: Zip/Unzip should use predicate variant when all inputs are masks #101598

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Test failure: JIT/opt/SVE/PredicateInstructions/PredicateInstructions.cmd #115988

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	GenTree* Compiler::gtNewSimdAllFalseMaskNode(unsigned simdSize)
	GenTree* Compiler::gtNewSimdFalseMaskByteNode(unsigned simdSize)

Add pattern matching for SVE intrinsics that operate on mask operands #114438

Add pattern matching for SVE intrinsics that operate on mask operands #114438

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