PowerPC: Implement PI interrupt for uncached unaligned writes

Source/Core/Core/PowerPC/MMU.cpp

@@ -18,6 +18,7 @@
 #include "Core/HW/GPFifo.h"
 #include "Core/HW/MMIO.h"
 #include "Core/HW/Memmap.h"
+#include "Core/HW/ProcessorInterface.h"
 #include "Core/PowerPC/JitInterface.h"
 #include "Core/PowerPC/PowerPC.h"
 
@@ -368,6 +369,9 @@ static void WriteToHardware(u32 em_address, const u32 data, const u32 size)
     // behavior for write-through/cache-inhibited writes with a start address or end address that
     // isn't 32-bit aligned. See https://bugs.dolphin-emu.org/issues/12565 for details.
 
+    // TODO: This interrupt is supposed to have associated cause and address registers
+    ProcessorInterface::SetInterrupt(ProcessorInterface::INT_CAUSE_PI);
+
     const u32 rotated_data = Common::RotateRight(data, ((em_address & 0x3) + size) * 8);
 
     for (u32 addr = em_address & ~0x7; addr < em_address + size; addr += 8)