New rules for compatibility with Verilog 2001

[DaveMcEwan]

This collection of simple new rules is to catch the easy mistakes when you need to write code compatible with IEEE1364-2001. Of course, it won't catch everything but it finds the most common things (in my experience).

• 2 renames:
  • non_ansi_module -> module_nonansi_forbidden
  • level_sensitive_always -> general_always_no_edge
• New rules:
  • module_ansi_forbidden
  • general_always_level_sensitive - Similar to general_always_no_edge but allows always @*.
  • operator_self_assignment - forbids +=, -=, etc.
  • operator_incdec - forbids ++ and --.
  • keyword_forbidden_logic
  • keyword_forbidden_always_comb, keyword_forbidden_always_ff, keyword_forbidden_always_latch
  • blocking_assignment_in_always_at_edge - Similar to blocking_assignment_in_always_comb but for always @(posedge clk).
  • non_blocking_assignment_in_always_no_edge - Similar to non_blocking_assignment_in_always_comb.
• And a new ruleset designintentV2001 to bring it all together.

[dalance]

Thanks!
All rules looks good.