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[GAS, ARM, 2/16] Add CLI extension support for Armv8.1-M Mainline
This patch implements the dsp, fp and fp.dp extensions for Armv8.1-M Mainline. This patch also removes the fp-armv8 check from the half-precision move instructions 'do_neon_movhf', as checking that the FP16 instructions extension feature bit is enabled 'ARM_EXT2_FP16_INST' is enough. gas/ChangeLog: 2019-04-15 Andre Vieira <[email protected]> * config/tc-arm.c (do_neon_movhf): Remove fp-armv8 check. (armv8_1m_main_ext_table): New extension table. (arm_archs): Use the new extension table. * doc/c-arm.texi: Add missing arch and document new extensions. * testsuite/gas/arm/armv8.1-m.main-fp.d: New. * testsuite/gas/arm/armv8.1-m.main-fp-dp.d: New. * testsuite/gas/arm/armv8.1-m.main-hp.d: New.
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‎gas/ChangeLog

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,13 @@
1+
2019-04-15 Andre Vieira <[email protected]>
2+
3+
* config/tc-arm.c (do_neon_movhf): Remove fp-armv8 check.
4+
(armv8_1m_main_ext_table): New extension table.
5+
(arm_archs): Use the new extension table.
6+
* doc/c-arm.texi: Add missing arch and document new extensions.
7+
* testsuite/gas/arm/armv8.1-m.main-fp.d: New.
8+
* testsuite/gas/arm/armv8.1-m.main-fp-dp.d: New.
9+
* testsuite/gas/arm/armv8.1-m.main-hp.d: New.
10+
111
2019-04-15 Thomas Preud'homme <[email protected]>
212

313
* config/tc-arm.c (cpu_arch_ver): Add entry for Armv8.1-M Mainline

‎gas/config/tc-arm.c

Lines changed: 16 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -16809,9 +16809,6 @@ do_neon_movhf (void)
1680916809
enum neon_shape rs = neon_select_shape (NS_HH, NS_NULL);
1681016810
constraint (rs != NS_HH, _("invalid suffix"));
1681116811

16812-
constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
16813-
_(BAD_FPU));
16814-
1681516812
if (inst.cond != COND_ALWAYS)
1681616813
{
1681716814
if (thumb_mode)
@@ -26503,6 +26500,20 @@ static const struct arm_ext_table armv8m_main_ext_table[] =
2650326500
{ NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
2650426501
};
2650526502

26503+
static const struct arm_ext_table armv8_1m_main_ext_table[] =
26504+
{
26505+
ARM_EXT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
26506+
ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP)),
26507+
ARM_EXT ("fp",
26508+
ARM_FEATURE (0, ARM_EXT2_FP16_INST,
26509+
FPU_VFP_V5_SP_D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA),
26510+
ALL_FP),
26511+
ARM_ADD ("fp.dp",
26512+
ARM_FEATURE (0, ARM_EXT2_FP16_INST,
26513+
FPU_VFP_V5D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)),
26514+
{ NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE }
26515+
};
26516+
2650626517
static const struct arm_ext_table armv8r_ext_table[] =
2650726518
{
2650826519
ARM_ADD ("crc", ARCH_CRC_ARMV8),
@@ -26570,7 +26581,8 @@ static const struct arm_arch_option_table arm_archs[] =
2657026581
ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE, FPU_ARCH_VFP),
2657126582
ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN, FPU_ARCH_VFP,
2657226583
armv8m_main),
26573-
ARM_ARCH_OPT ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN, FPU_ARCH_VFP),
26584+
ARM_ARCH_OPT2 ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN, FPU_ARCH_VFP,
26585+
armv8_1m_main),
2657426586
ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP, armv8a),
2657526587
ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A, FPU_ARCH_VFP, armv81a),
2657626588
ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A, FPU_ARCH_VFP, armv82a),

‎gas/doc/c-arm.texi

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -250,6 +250,7 @@ names are recognized:
250250
@code{armv8.5-a},
251251
@code{armv8-m.base},
252252
@code{armv8-m.main},
253+
@code{armv8.1-m.main},
253254
@code{iwmmxt},
254255
@code{iwmmxt2}
255256
and
@@ -355,6 +356,16 @@ double-word registers.
355356
@code{+nofp}: Disables all FPU instructions.
356357
@code{+nodsp}: Disables DSP Extension.
357358

359+
For @code{armv8.1-m.main}:
360+
361+
@code{+dsp}: Enables DSP Extension.
362+
@code{+fp}: Enables single and half precision scalar Floating Point Extensions
363+
for Armv8.1-M Mainline with 16 double-word registers.
364+
@code{+fp.dp}: Enables double precision scalar Floating Point Extensions for
365+
Armv8.1-M Mainline, implies @code{+fp}.
366+
@code{+nofp}: Disables all FPU instructions.
367+
@code{+nodsp}: Disables DSP Extension.
368+
358369
For @code{armv8-a}:
359370

360371
@code{+crc}: Enables CRC32 Extension.

‎gas/testsuite/gas/arm/armv8.1-m.main-fp-dp.d

Lines changed: 203 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,203 @@
1+
# name: Double precision instructions for 'armv8.1-m.main'
2+
# source: vfp1_t2.s
3+
# as: -march=armv8.1-m.main+fp.dp
4+
# objdump: -dr --prefix-addresses --show-raw-insn
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6+
.*: +file format .*arm.*
7+
8+
Disassembly of section .text:
9+
0+000 <[^>]*> eeb4 0bc0 (vcmpe\.f64|fcmped) d0, d0
10+
0+004 <[^>]*> eeb5 0bc0 (vcmpe\.f64 d0, #0.0|fcmpezd d0)
11+
0+008 <[^>]*> eeb4 0b40 (vcmp\.f64|fcmpd) d0, d0
12+
0+00c <[^>]*> eeb5 0b40 (vcmp\.f64 d0, #0.0|fcmpzd d0)
13+
0+010 <[^>]*> eeb0 0bc0 (vabs\.f64|fabsd) d0, d0
14+
0+014 <[^>]*> eeb0 0b40 (vmov\.f64|fcpyd) d0, d0
15+
0+018 <[^>]*> eeb1 0b40 (vneg\.f64|fnegd) d0, d0
16+
0+01c <[^>]*> eeb1 0bc0 (vsqrt\.f64|fsqrtd) d0, d0
17+
0+020 <[^>]*> ee30 0b00 (vadd\.f64|faddd) d0, d0, d0
18+
0+024 <[^>]*> ee80 0b00 (vdiv\.f64|fdivd) d0, d0, d0
19+
0+028 <[^>]*> ee00 0b00 (vmla\.f64|fmacd) d0, d0, d0
20+
0+02c <[^>]*> ee10 0b00 (vnmls\.f64|fmscd) d0, d0, d0
21+
0+030 <[^>]*> ee20 0b00 (vmul\.f64|fmuld) d0, d0, d0
22+
0+034 <[^>]*> ee00 0b40 (vmls\.f64|fnmacd) d0, d0, d0
23+
0+038 <[^>]*> ee10 0b40 (vnmla\.f64|fnmscd) d0, d0, d0
24+
0+03c <[^>]*> ee20 0b40 (vnmul\.f64|fnmuld) d0, d0, d0
25+
0+040 <[^>]*> ee30 0b40 (vsub\.f64|fsubd) d0, d0, d0
26+
0+044 <[^>]*> ed90 0b00 vldr d0, \[r0\]
27+
0+048 <[^>]*> ed80 0b00 vstr d0, \[r0\]
28+
0+04c <[^>]*> ec90 0b02 vldmia r0, {d0}
29+
0+050 <[^>]*> ec90 0b02 vldmia r0, {d0}
30+
0+054 <[^>]*> ecb0 0b02 vldmia r0!, {d0}
31+
0+058 <[^>]*> ecb0 0b02 vldmia r0!, {d0}
32+
0+05c <[^>]*> ed30 0b02 vldmdb r0!, {d0}
33+
0+060 <[^>]*> ed30 0b02 vldmdb r0!, {d0}
34+
0+064 <[^>]*> ec80 0b02 vstmia r0, {d0}
35+
0+068 <[^>]*> ec80 0b02 vstmia r0, {d0}
36+
0+06c <[^>]*> eca0 0b02 vstmia r0!, {d0}
37+
0+070 <[^>]*> eca0 0b02 vstmia r0!, {d0}
38+
0+074 <[^>]*> ed20 0b02 vstmdb r0!, {d0}
39+
0+078 <[^>]*> ed20 0b02 vstmdb r0!, {d0}
40+
0+07c <[^>]*> eeb8 0bc0 (vcvt\.f64\.s32|fsitod) d0, s0
41+
0+080 <[^>]*> eeb8 0b40 (vcvt\.f64\.u32|fuitod) d0, s0
42+
0+084 <[^>]*> eebd 0b40 (vcvtr\.s32\.f64|ftosid) s0, d0
43+
0+088 <[^>]*> eebd 0bc0 (vcvt\.s32\.f64|ftosizd) s0, d0
44+
0+08c <[^>]*> eebc 0b40 (vcvtr\.u32\.f64|ftouid) s0, d0
45+
0+090 <[^>]*> eebc 0bc0 (vcvt\.u32\.f64|ftouizd) s0, d0
46+
0+094 <[^>]*> eeb7 0ac0 (vcvt\.f64\.f32|fcvtds) d0, s0
47+
0+098 <[^>]*> eeb7 0bc0 (vcvt\.f32\.f64|fcvtsd) s0, d0
48+
0+09c <[^>]*> ee30 0b10 vmov\.32 r0, d0\[1\]
49+
0+0a0 <[^>]*> ee10 0b10 vmov\.32 r0, d0\[0\]
50+
0+0a4 <[^>]*> ee20 0b10 vmov\.32 d0\[1\], r0
51+
0+0a8 <[^>]*> ee00 0b10 vmov\.32 d0\[0\], r0
52+
0+0ac <[^>]*> eeb5 1b40 (vcmp\.f64 d1, #0.0|fcmpzd d1)
53+
0+0b0 <[^>]*> eeb5 2b40 (vcmp\.f64 d2, #0.0|fcmpzd d2)
54+
0+0b4 <[^>]*> eeb5 fb40 (vcmp\.f64 d15, #0.0|fcmpzd d15)
55+
0+0b8 <[^>]*> eeb4 0b41 (vcmp\.f64|fcmpd) d0, d1
56+
0+0bc <[^>]*> eeb4 0b42 (vcmp\.f64|fcmpd) d0, d2
57+
0+0c0 <[^>]*> eeb4 0b4f (vcmp\.f64|fcmpd) d0, d15
58+
0+0c4 <[^>]*> eeb4 1b40 (vcmp\.f64|fcmpd) d1, d0
59+
0+0c8 <[^>]*> eeb4 2b40 (vcmp\.f64|fcmpd) d2, d0
60+
0+0cc <[^>]*> eeb4 fb40 (vcmp\.f64|fcmpd) d15, d0
61+
0+0d0 <[^>]*> eeb4 5b4c (vcmp\.f64|fcmpd) d5, d12
62+
0+0d4 <[^>]*> eeb1 0b41 (vneg\.f64|fnegd) d0, d1
63+
0+0d8 <[^>]*> eeb1 0b42 (vneg\.f64|fnegd) d0, d2
64+
0+0dc <[^>]*> eeb1 0b4f (vneg\.f64|fnegd) d0, d15
65+
0+0e0 <[^>]*> eeb1 1b40 (vneg\.f64|fnegd) d1, d0
66+
0+0e4 <[^>]*> eeb1 2b40 (vneg\.f64|fnegd) d2, d0
67+
0+0e8 <[^>]*> eeb1 fb40 (vneg\.f64|fnegd) d15, d0
68+
0+0ec <[^>]*> eeb1 cb45 (vneg\.f64|fnegd) d12, d5
69+
0+0f0 <[^>]*> ee30 0b01 (vadd\.f64|faddd) d0, d0, d1
70+
0+0f4 <[^>]*> ee30 0b02 (vadd\.f64|faddd) d0, d0, d2
71+
0+0f8 <[^>]*> ee30 0b0f (vadd\.f64|faddd) d0, d0, d15
72+
0+0fc <[^>]*> ee31 0b00 (vadd\.f64|faddd) d0, d1, d0
73+
0+100 <[^>]*> ee32 0b00 (vadd\.f64|faddd) d0, d2, d0
74+
0+104 <[^>]*> ee3f 0b00 (vadd\.f64|faddd) d0, d15, d0
75+
0+108 <[^>]*> ee30 1b00 (vadd\.f64|faddd) d1, d0, d0
76+
0+10c <[^>]*> ee30 2b00 (vadd\.f64|faddd) d2, d0, d0
77+
0+110 <[^>]*> ee30 fb00 (vadd\.f64|faddd) d15, d0, d0
78+
0+114 <[^>]*> ee39 cb05 (vadd\.f64|faddd) d12, d9, d5
79+
0+118 <[^>]*> eeb7 0ae0 (vcvt\.f64\.f32|fcvtds) d0, s1
80+
0+11c <[^>]*> eeb7 0ac1 (vcvt\.f64\.f32|fcvtds) d0, s2
81+
0+120 <[^>]*> eeb7 0aef (vcvt\.f64\.f32|fcvtds) d0, s31
82+
0+124 <[^>]*> eeb7 1ac0 (vcvt\.f64\.f32|fcvtds) d1, s0
83+
0+128 <[^>]*> eeb7 2ac0 (vcvt\.f64\.f32|fcvtds) d2, s0
84+
0+12c <[^>]*> eeb7 fac0 (vcvt\.f64\.f32|fcvtds) d15, s0
85+
0+130 <[^>]*> eef7 0bc0 (vcvt\.f32\.f64|fcvtsd) s1, d0
86+
0+134 <[^>]*> eeb7 1bc0 (vcvt\.f32\.f64|fcvtsd) s2, d0
87+
0+138 <[^>]*> eef7 fbc0 (vcvt\.f32\.f64|fcvtsd) s31, d0
88+
0+13c <[^>]*> eeb7 0bc1 (vcvt\.f32\.f64|fcvtsd) s0, d1
89+
0+140 <[^>]*> eeb7 0bc2 (vcvt\.f32\.f64|fcvtsd) s0, d2
90+
0+144 <[^>]*> eeb7 0bcf (vcvt\.f32\.f64|fcvtsd) s0, d15
91+
0+148 <[^>]*> ee30 1b10 vmov\.32 r1, d0\[1\]
92+
0+14c <[^>]*> ee30 eb10 vmov\.32 lr, d0\[1\]
93+
0+150 <[^>]*> ee31 0b10 vmov\.32 r0, d1\[1\]
94+
0+154 <[^>]*> ee32 0b10 vmov\.32 r0, d2\[1\]
95+
0+158 <[^>]*> ee3f 0b10 vmov\.32 r0, d15\[1\]
96+
0+15c <[^>]*> ee10 1b10 vmov\.32 r1, d0\[0\]
97+
0+160 <[^>]*> ee10 eb10 vmov\.32 lr, d0\[0\]
98+
0+164 <[^>]*> ee11 0b10 vmov\.32 r0, d1\[0\]
99+
0+168 <[^>]*> ee12 0b10 vmov\.32 r0, d2\[0\]
100+
0+16c <[^>]*> ee1f 0b10 vmov\.32 r0, d15\[0\]
101+
0+170 <[^>]*> ee20 1b10 vmov\.32 d0\[1\], r1
102+
0+174 <[^>]*> ee20 eb10 vmov\.32 d0\[1\], lr
103+
0+178 <[^>]*> ee21 0b10 vmov\.32 d1\[1\], r0
104+
0+17c <[^>]*> ee22 0b10 vmov\.32 d2\[1\], r0
105+
0+180 <[^>]*> ee2f 0b10 vmov\.32 d15\[1\], r0
106+
0+184 <[^>]*> ee00 1b10 vmov\.32 d0\[0\], r1
107+
0+188 <[^>]*> ee00 eb10 vmov\.32 d0\[0\], lr
108+
0+18c <[^>]*> ee01 0b10 vmov\.32 d1\[0\], r0
109+
0+190 <[^>]*> ee02 0b10 vmov\.32 d2\[0\], r0
110+
0+194 <[^>]*> ee0f 0b10 vmov\.32 d15\[0\], r0
111+
0+198 <[^>]*> ed91 0b00 vldr d0, \[r1\]
112+
0+19c <[^>]*> ed9e 0b00 vldr d0, \[lr\]
113+
0+1a0 <[^>]*> ed90 0b00 vldr d0, \[r0\]
114+
0+1a4 <[^>]*> ed90 0bff vldr d0, \[r0, #1020\].*
115+
0+1a8 <[^>]*> ed10 0bff vldr d0, \[r0, #-1020\].*
116+
0+1ac <[^>]*> ed90 1b00 vldr d1, \[r0\]
117+
0+1b0 <[^>]*> ed90 2b00 vldr d2, \[r0\]
118+
0+1b4 <[^>]*> ed90 fb00 vldr d15, \[r0\]
119+
0+1b8 <[^>]*> ed8c cbc9 vstr d12, \[ip, #804\].*
120+
0+1bc <[^>]*> ec90 1b02 vldmia r0, {d1}
121+
0+1c0 <[^>]*> ec90 2b02 vldmia r0, {d2}
122+
0+1c4 <[^>]*> ec90 fb02 vldmia r0, {d15}
123+
0+1c8 <[^>]*> ec90 0b04 vldmia r0, {d0-d1}
124+
0+1cc <[^>]*> ec90 0b06 vldmia r0, {d0-d2}
125+
0+1d0 <[^>]*> ec90 0b20 vldmia r0, {d0-d15}
126+
0+1d4 <[^>]*> ec90 1b1e vldmia r0, {d1-d15}
127+
0+1d8 <[^>]*> ec90 2b1c vldmia r0, {d2-d15}
128+
0+1dc <[^>]*> ec90 eb04 vldmia r0, {d14-d15}
129+
0+1e0 <[^>]*> ec91 0b02 vldmia r1, {d0}
130+
0+1e4 <[^>]*> ec9e 0b02 vldmia lr, {d0}
131+
0+1e8 <[^>]*> eeb5 0b40 (vcmp\.f64 d0, #0.0|fcmpzd d0)
132+
0+1ec <[^>]*> eeb5 1b40 (vcmp\.f64 d1, #0.0|fcmpzd d1)
133+
0+1f0 <[^>]*> eeb5 2b40 (vcmp\.f64 d2, #0.0|fcmpzd d2)
134+
0+1f4 <[^>]*> eeb5 3b40 (vcmp\.f64 d3, #0.0|fcmpzd d3)
135+
0+1f8 <[^>]*> eeb5 4b40 (vcmp\.f64 d4, #0.0|fcmpzd d4)
136+
0+1fc <[^>]*> eeb5 5b40 (vcmp\.f64 d5, #0.0|fcmpzd d5)
137+
0+200 <[^>]*> eeb5 6b40 (vcmp\.f64 d6, #0.0|fcmpzd d6)
138+
0+204 <[^>]*> eeb5 7b40 (vcmp\.f64 d7, #0.0|fcmpzd d7)
139+
0+208 <[^>]*> eeb5 8b40 (vcmp\.f64 d8, #0.0|fcmpzd d8)
140+
0+20c <[^>]*> eeb5 9b40 (vcmp\.f64 d9, #0.0|fcmpzd d9)
141+
0+210 <[^>]*> eeb5 ab40 (vcmp\.f64 d10, #0.0|fcmpzd d10)
142+
0+214 <[^>]*> eeb5 bb40 (vcmp\.f64 d11, #0.0|fcmpzd d11)
143+
0+218 <[^>]*> eeb5 cb40 (vcmp\.f64 d12, #0.0|fcmpzd d12)
144+
0+21c <[^>]*> eeb5 db40 (vcmp\.f64 d13, #0.0|fcmpzd d13)
145+
0+220 <[^>]*> eeb5 eb40 (vcmp\.f64 d14, #0.0|fcmpzd d14)
146+
0+224 <[^>]*> eeb5 fb40 (vcmp\.f64 d15, #0.0|fcmpzd d15)
147+
0+228 <[^>]*> bf01 itttt eq
148+
0+22a <[^>]*> eeb4 1bcf (vcmpeeq\.f64|fcmpedeq) d1, d15
149+
0+22e <[^>]*> eeb5 2bc0 (vcmpeeq\.f64 d2, #0.0|fcmpezdeq d2)
150+
0+232 <[^>]*> eeb4 3b4e (vcmpeq\.f64|fcmpdeq) d3, d14
151+
0+236 <[^>]*> eeb5 4b40 (vcmpeq\.f64 d4, #0.0|fcmpzdeq d4)
152+
0+23a <[^>]*> bf01 itttt eq
153+
0+23c <[^>]*> eeb0 5bcd (vabseq\.f64|fabsdeq) d5, d13
154+
0+240 <[^>]*> eeb0 6b4c (vmoveq\.f64|fcpydeq) d6, d12
155+
0+244 <[^>]*> eeb1 7b4b (vnegeq\.f64|fnegdeq) d7, d11
156+
0+248 <[^>]*> eeb1 8bca (vsqrteq\.f64|fsqrtdeq) d8, d10
157+
0+24c <[^>]*> bf01 itttt eq
158+
0+24e <[^>]*> ee31 9b0f (vaddeq\.f64|fadddeq) d9, d1, d15
159+
0+252 <[^>]*> ee83 2b0e (vdiveq\.f64|fdivdeq) d2, d3, d14
160+
0+256 <[^>]*> ee0d 4b0c (vmlaeq\.f64|fmacdeq) d4, d13, d12
161+
0+25a <[^>]*> ee16 5b0b (vnmlseq\.f64|fmscdeq) d5, d6, d11
162+
0+25e <[^>]*> bf01 itttt eq
163+
0+260 <[^>]*> ee2a 7b09 (vmuleq\.f64|fmuldeq) d7, d10, d9
164+
0+264 <[^>]*> ee09 8b4a (vmlseq\.f64|fnmacdeq) d8, d9, d10
165+
0+268 <[^>]*> ee16 7b4b (vnmlaeq\.f64|fnmscdeq) d7, d6, d11
166+
0+26c <[^>]*> ee24 5b4c (vnmuleq\.f64|fnmuldeq) d5, d4, d12
167+
0+270 <[^>]*> bf02 ittt eq
168+
0+272 <[^>]*> ee3d 3b4e (vsubeq\.f64|fsubdeq) d3, d13, d14
169+
0+276 <[^>]*> ed95 2b00 vldreq d2, \[r5\]
170+
0+27a <[^>]*> ed8c 1b00 vstreq d1, \[ip\]
171+
0+27e <[^>]*> bf01 itttt eq
172+
0+280 <[^>]*> ec91 1b02 vldmiaeq r1, {d1}
173+
0+284 <[^>]*> ec92 2b02 vldmiaeq r2, {d2}
174+
0+288 <[^>]*> ecb3 3b02 vldmiaeq r3!, {d3}
175+
0+28c <[^>]*> ecb4 4b02 vldmiaeq r4!, {d4}
176+
0+290 <[^>]*> bf01 itttt eq
177+
0+292 <[^>]*> ed35 5b02 vldmdbeq r5!, {d5}
178+
0+296 <[^>]*> ed36 6b02 vldmdbeq r6!, {d6}
179+
0+29a <[^>]*> ec87 fb02 vstmiaeq r7, {d15}
180+
0+29e <[^>]*> ec88 eb02 vstmiaeq r8, {d14}
181+
0+2a2 <[^>]*> bf01 itttt eq
182+
0+2a4 <[^>]*> eca9 db02 vstmiaeq r9!, {d13}
183+
0+2a8 <[^>]*> ecaa cb02 vstmiaeq sl!, {d12}
184+
0+2ac <[^>]*> ed2b bb02 vstmdbeq fp!, {d11}
185+
0+2b0 <[^>]*> ed2c ab02 vstmdbeq ip!, {d10}
186+
0+2b4 <[^>]*> bf01 itttt eq
187+
0+2b6 <[^>]*> eeb8 fbe0 (vcvteq\.f64\.s32|fsitodeq) d15, s1
188+
0+2ba <[^>]*> eeb8 1b6f (vcvteq\.f64\.u32|fuitodeq) d1, s31
189+
0+2be <[^>]*> eefd 0b4f (vcvtreq\.s32\.f64|ftosideq) s1, d15
190+
0+2c2 <[^>]*> eefd fbc2 (vcvteq\.s32\.f64|ftosizdeq) s31, d2
191+
0+2c6 <[^>]*> bf01 itttt eq
192+
0+2c8 <[^>]*> eefc 7b42 (vcvtreq\.u32\.f64|ftouideq) s15, d2
193+
0+2cc <[^>]*> eefc 5bc3 (vcvteq\.u32\.f64|ftouizdeq) s11, d3
194+
0+2d0 <[^>]*> eeb7 1ac5 (vcvteq\.f64\.f32|fcvtdseq) d1, s10
195+
0+2d4 <[^>]*> eef7 5bc1 (vcvteq\.f32\.f64|fcvtsdeq) s11, d1
196+
0+2d8 <[^>]*> bf01 itttt eq
197+
0+2da <[^>]*> ee31 8b10 vmoveq\.32 r8, d1\[1\]
198+
0+2de <[^>]*> ee1f 7b10 vmoveq\.32 r7, d15\[0\]
199+
0+2e2 <[^>]*> ee21 fb10 vmoveq\.32 d1\[1\], pc
200+
0+2e6 <[^>]*> ee0f 1b10 vmoveq\.32 d15\[0\], r1
201+
0+2ea <[^>]*> bf00 nop
202+
0+2ec <[^>]*> bf00 nop
203+
0+2ee <[^>]*> bf00 nop

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