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[binutils, ARM, 1/16] Add support for Armv8.1-M Mainline CLI
The patch is straightforward, it does the following: - support the new Tag_CPU_arch build attribute value, ie.: + declare the new value + update all the asserts forcing logic to be reviewed for new architectures + create a corresponding bfd_mach_arm_8_1M_MAIN enumerator in bfd and add mapping from Tag_CPU_arch to it + teach readelf about new Tag_CPU_arch value - declare armv8.1-m.main as a supported architecture value - define Armv8.1-M Mainline in terms of feature bits available - tell objdump mapping from bfd_mach_arm_8_1M_MAIN enumerator to feature bits available - update architecture-specific logic in gas and bfd guarded by the asserts mentioned above. - tests for all the above ChangeLog entries are as follows: *** bfd/ChangeLog *** 2019-04-15 Thomas Preud'homme <[email protected]> * archures.c (bfd_mach_arm_8_1M_MAIN): Define. * bfd-in2.h: Regenerate. * cpu-arm.c (arch_info_struct): Add entry for Armv8.1-M Mainline. * elf32-arm.c (using_thumb_only): Return true for Armv8.1-M Mainline and update assert. (using_thumb2): Likewise. (using_thumb2_bl): Update assert. (arch_has_arm_nop): Likewise. (bfd_arm_get_mach_from_attributes): Add case for Armv8.1-M Mainline. (tag_cpu_arch_combine): Add logic for Armv8.1-M Mainline merging. *** binutils/ChangeLog *** 2019-04-15 Thomas Preud'homme <[email protected]> * readelf.c (arm_attr_tag_CPU_arch): Add entry for Armv8.1-M Mainline. *** gas/ChangeLog *** 2019-04-15 Thomas Preud'homme <[email protected]> * config/tc-arm.c (cpu_arch_ver): Add entry for Armv8.1-M Mainline Tag_CPU_arch build attribute value. Reindent. (get_aeabi_cpu_arch_from_fset): Update assert. (aeabi_set_public_attributes): Update assert for Tag_DIV_use logic. * testsuite/gas/arm/attr-march-armv8_1-m.main.d: New test. *** include/ChangeLog *** 2019-04-15 Thomas Preud'homme <[email protected]> * elf/arm.h (TAG_CPU_ARCH_V8_1M_MAIN): new macro. (MAX_TAG_CPU_ARCH): Set value to above macro. * opcode/arm.h (ARM_EXT2_V8_1M_MAIN): New macro. (ARM_AEXT_V8_1M_MAIN): Likewise. (ARM_AEXT2_V8_1M_MAIN): Likewise. (ARM_ARCH_V8_1M_MAIN): Likewise. *** ld/ChangeLog *** 2019-04-15 Thomas Preud'homme <[email protected]> * testsuite/ld-arm/attr-merge-13.attr: New test. * testsuite/ld-arm/attr-merge-13a.s: New test. * testsuite/ld-arm/attr-merge-13b.s: New test. *** opcodes/ChangeLog *** 2019-04-15 Thomas Preud'homme <[email protected]> * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
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‎bfd/ChangeLog

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,16 @@
1+
2019-04-15 Thomas Preud'homme <[email protected]>
2+
3+
* archures.c (bfd_mach_arm_8_1M_MAIN): Define.
4+
* bfd-in2.h: Regenerate.
5+
* cpu-arm.c (arch_info_struct): Add entry for Armv8.1-M Mainline.
6+
* elf32-arm.c (using_thumb_only): Return true for Armv8.1-M Mainline
7+
and update assert.
8+
(using_thumb2): Likewise.
9+
(using_thumb2_bl): Update assert.
10+
(arch_has_arm_nop): Likewise.
11+
(bfd_arm_get_mach_from_attributes): Add case for Armv8.1-M Mainline.
12+
(tag_cpu_arch_combine): Add logic for Armv8.1-M Mainline merging.
13+
114
2019-04-11 H.J. Lu <[email protected]>
215

316
* elf-linker-x86.h (elf_x86_cet_report): New.

‎bfd/archures.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -341,6 +341,7 @@ DESCRIPTION
341341
.#define bfd_mach_arm_8R 24
342342
.#define bfd_mach_arm_8M_BASE 25
343343
.#define bfd_mach_arm_8M_MAIN 26
344+
.#define bfd_mach_arm_8_1M_MAIN 27
344345
. bfd_arch_nds32, {* Andes NDS32. *}
345346
.#define bfd_mach_n1 1
346347
.#define bfd_mach_n1h 2

‎bfd/bfd-in2.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2274,6 +2274,7 @@ enum bfd_architecture
22742274
#define bfd_mach_arm_8R 24
22752275
#define bfd_mach_arm_8M_BASE 25
22762276
#define bfd_mach_arm_8M_MAIN 26
2277+
#define bfd_mach_arm_8_1M_MAIN 27
22772278
bfd_arch_nds32, /* Andes NDS32. */
22782279
#define bfd_mach_n1 1
22792280
#define bfd_mach_n1h 2

‎bfd/cpu-arm.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -248,6 +248,7 @@ static const bfd_arch_info_type arch_info_struct[] =
248248
N (bfd_mach_arm_8R, "armv8-r", FALSE, & arch_info_struct[24]),
249249
N (bfd_mach_arm_8M_BASE, "armv8-m.base", FALSE, & arch_info_struct[25]),
250250
N (bfd_mach_arm_8M_MAIN, "armv8-m.main", FALSE, & arch_info_struct[26]),
251+
N (bfd_mach_arm_8_1M_MAIN, "armv8.1-m.main", FALSE, & arch_info_struct[27]),
251252
N (bfd_mach_arm_unknown, "arm_any", FALSE, NULL)
252253
};
253254

‎bfd/elf32-arm.c

Lines changed: 43 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -3835,13 +3835,14 @@ using_thumb_only (struct elf32_arm_link_hash_table *globals)
38353835
arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
38363836

38373837
/* Force return logic to be reviewed for each new architecture. */
3838-
BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
3838+
BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
38393839

38403840
if (arch == TAG_CPU_ARCH_V6_M
38413841
|| arch == TAG_CPU_ARCH_V6S_M
38423842
|| arch == TAG_CPU_ARCH_V7E_M
38433843
|| arch == TAG_CPU_ARCH_V8M_BASE
3844-
|| arch == TAG_CPU_ARCH_V8M_MAIN)
3844+
|| arch == TAG_CPU_ARCH_V8M_MAIN
3845+
|| arch == TAG_CPU_ARCH_V8_1M_MAIN)
38453846
return TRUE;
38463847

38473848
return FALSE;
@@ -3862,14 +3863,15 @@ using_thumb2 (struct elf32_arm_link_hash_table *globals)
38623863
arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
38633864

38643865
/* Force return logic to be reviewed for each new architecture. */
3865-
BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
3866+
BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
38663867

38673868
return (arch == TAG_CPU_ARCH_V6T2
38683869
|| arch == TAG_CPU_ARCH_V7
38693870
|| arch == TAG_CPU_ARCH_V7E_M
38703871
|| arch == TAG_CPU_ARCH_V8
38713872
|| arch == TAG_CPU_ARCH_V8R
3872-
|| arch == TAG_CPU_ARCH_V8M_MAIN);
3873+
|| arch == TAG_CPU_ARCH_V8M_MAIN
3874+
|| arch == TAG_CPU_ARCH_V8_1M_MAIN);
38733875
}
38743876

38753877
/* Determine whether Thumb-2 BL instruction is available. */
@@ -3881,7 +3883,7 @@ using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
38813883
bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
38823884

38833885
/* Force return logic to be reviewed for each new architecture. */
3884-
BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
3886+
BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
38853887

38863888
/* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
38873889
return (arch == TAG_CPU_ARCH_V6T2
@@ -4101,7 +4103,7 @@ arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
41014103
Tag_CPU_arch);
41024104

41034105
/* Force return logic to be reviewed for each new architecture. */
4104-
BFD_ASSERT (arch <= TAG_CPU_ARCH_V8M_MAIN);
4106+
BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
41054107

41064108
return (arch == TAG_CPU_ARCH_V6T2
41074109
|| arch == TAG_CPU_ARCH_V6K
@@ -13719,6 +13721,8 @@ bfd_arm_get_mach_from_attributes (bfd * abfd)
1371913721
return bfd_mach_arm_8M_BASE;
1372013722
case TAG_CPU_ARCH_V8M_MAIN:
1372113723
return bfd_mach_arm_8M_MAIN;
13724+
case TAG_CPU_ARCH_V8_1M_MAIN:
13725+
return bfd_mach_arm_8_1M_MAIN;
1372213726

1372313727
default:
1372413728
/* Force entry to be added for any new known Tag_CPU_arch value. */
@@ -14131,6 +14135,31 @@ tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
1413114135
T(V8M_MAIN), /* V8-M BASELINE. */
1413214136
T(V8M_MAIN) /* V8-M MAINLINE. */
1413314137
};
14138+
const int v8_1m_mainline[] =
14139+
{
14140+
-1, /* PRE_V4. */
14141+
-1, /* V4. */
14142+
-1, /* V4T. */
14143+
-1, /* V5T. */
14144+
-1, /* V5TE. */
14145+
-1, /* V5TEJ. */
14146+
-1, /* V6. */
14147+
-1, /* V6KZ. */
14148+
-1, /* V6T2. */
14149+
-1, /* V6K. */
14150+
T(V8_1M_MAIN), /* V7. */
14151+
T(V8_1M_MAIN), /* V6_M. */
14152+
T(V8_1M_MAIN), /* V6S_M. */
14153+
T(V8_1M_MAIN), /* V7E_M. */
14154+
-1, /* V8. */
14155+
-1, /* V8R. */
14156+
T(V8_1M_MAIN), /* V8-M BASELINE. */
14157+
T(V8_1M_MAIN), /* V8-M MAINLINE. */
14158+
-1, /* Unused (18). */
14159+
-1, /* Unused (19). */
14160+
-1, /* Unused (20). */
14161+
T(V8_1M_MAIN) /* V8.1-M MAINLINE. */
14162+
};
1413414163
const int v4t_plus_v6_m[] =
1413514164
{
1413614165
-1, /* PRE_V4. */
@@ -14151,6 +14180,10 @@ tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
1415114180
-1, /* V8R. */
1415214181
T(V8M_BASE), /* V8-M BASELINE. */
1415314182
T(V8M_MAIN), /* V8-M MAINLINE. */
14183+
-1, /* Unused (18). */
14184+
-1, /* Unused (19). */
14185+
-1, /* Unused (20). */
14186+
T(V8_1M_MAIN), /* V8.1-M MAINLINE. */
1415414187
T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
1415514188
};
1415614189
const int *comb[] =
@@ -14165,6 +14198,10 @@ tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
1416514198
v8r,
1416614199
v8m_baseline,
1416714200
v8m_mainline,
14201+
NULL,
14202+
NULL,
14203+
NULL,
14204+
v8_1m_mainline,
1416814205
/* Pseudo-architecture. */
1416914206
v4t_plus_v6_m
1417014207
};

‎binutils/ChangeLog

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,7 @@
1+
2019-04-15 Thomas Preud'homme <[email protected]>
2+
3+
* readelf.c (arm_attr_tag_CPU_arch): Add entry for Armv8.1-M Mainline.
4+
15
2019-04-08 H.J. Lu <[email protected]>
26

37
* readelf.c (decode_x86_isa): Handle

‎binutils/readelf.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14370,7 +14370,7 @@ typedef struct
1437014370
static const char * arm_attr_tag_CPU_arch[] =
1437114371
{"Pre-v4", "v4", "v4T", "v5T", "v5TE", "v5TEJ", "v6", "v6KZ", "v6T2",
1437214372
"v6K", "v7", "v6-M", "v6S-M", "v7E-M", "v8", "v8-R", "v8-M.baseline",
14373-
"v8-M.mainline"};
14373+
"v8-M.mainline", "", "", "", "v8.1-M.mainline"};
1437414374
static const char * arm_attr_tag_ARM_ISA_use[] = {"No", "Yes"};
1437514375
static const char * arm_attr_tag_THUMB_ISA_use[] =
1437614376
{"No", "Thumb-1", "Thumb-2", "Yes"};

‎gas/ChangeLog

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,11 @@
1+
2019-04-15 Thomas Preud'homme <[email protected]>
2+
3+
* config/tc-arm.c (cpu_arch_ver): Add entry for Armv8.1-M Mainline
4+
Tag_CPU_arch build attribute value. Reindent.
5+
(get_aeabi_cpu_arch_from_fset): Update assert.
6+
(aeabi_set_public_attributes): Update assert for Tag_DIV_use logic.
7+
* testsuite/gas/arm/attr-march-armv8_1-m.main.d: New test.
8+
19
2019-04-09 Matthew Fortune <[email protected]>
210

311
* config/tc-mips.c (mips_cpu_info_table): Add i6500. Update

‎gas/config/tc-arm.c

Lines changed: 47 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -26570,6 +26570,7 @@ static const struct arm_arch_option_table arm_archs[] =
2657026570
ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE, FPU_ARCH_VFP),
2657126571
ARM_ARCH_OPT2 ("armv8-m.main", ARM_ARCH_V8M_MAIN, FPU_ARCH_VFP,
2657226572
armv8m_main),
26573+
ARM_ARCH_OPT ("armv8.1-m.main", ARM_ARCH_V8_1M_MAIN, FPU_ARCH_VFP),
2657326574
ARM_ARCH_OPT2 ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP, armv8a),
2657426575
ARM_ARCH_OPT2 ("armv8.1-a", ARM_ARCH_V8_1A, FPU_ARCH_VFP, armv81a),
2657526576
ARM_ARCH_OPT2 ("armv8.2-a", ARM_ARCH_V8_2A, FPU_ARCH_VFP, armv82a),
@@ -27284,30 +27285,30 @@ typedef struct
2728427285
stable when new architectures are added. */
2728527286
static const cpu_arch_ver_table cpu_arch_ver[] =
2728627287
{
27287-
{TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V1},
27288-
{TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2},
27289-
{TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2S},
27290-
{TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3},
27291-
{TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3M},
27292-
{TAG_CPU_ARCH_V4, ARM_ARCH_V4xM},
27293-
{TAG_CPU_ARCH_V4, ARM_ARCH_V4},
27294-
{TAG_CPU_ARCH_V4T, ARM_ARCH_V4TxM},
27295-
{TAG_CPU_ARCH_V4T, ARM_ARCH_V4T},
27296-
{TAG_CPU_ARCH_V5T, ARM_ARCH_V5xM},
27297-
{TAG_CPU_ARCH_V5T, ARM_ARCH_V5},
27298-
{TAG_CPU_ARCH_V5T, ARM_ARCH_V5TxM},
27299-
{TAG_CPU_ARCH_V5T, ARM_ARCH_V5T},
27300-
{TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TExP},
27301-
{TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TE},
27302-
{TAG_CPU_ARCH_V5TEJ, ARM_ARCH_V5TEJ},
27303-
{TAG_CPU_ARCH_V6, ARM_ARCH_V6},
27304-
{TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6Z},
27305-
{TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6KZ},
27306-
{TAG_CPU_ARCH_V6K, ARM_ARCH_V6K},
27307-
{TAG_CPU_ARCH_V6T2, ARM_ARCH_V6T2},
27308-
{TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KT2},
27309-
{TAG_CPU_ARCH_V6T2, ARM_ARCH_V6ZT2},
27310-
{TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KZT2},
27288+
{TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V1},
27289+
{TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2},
27290+
{TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V2S},
27291+
{TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3},
27292+
{TAG_CPU_ARCH_PRE_V4, ARM_ARCH_V3M},
27293+
{TAG_CPU_ARCH_V4, ARM_ARCH_V4xM},
27294+
{TAG_CPU_ARCH_V4, ARM_ARCH_V4},
27295+
{TAG_CPU_ARCH_V4T, ARM_ARCH_V4TxM},
27296+
{TAG_CPU_ARCH_V4T, ARM_ARCH_V4T},
27297+
{TAG_CPU_ARCH_V5T, ARM_ARCH_V5xM},
27298+
{TAG_CPU_ARCH_V5T, ARM_ARCH_V5},
27299+
{TAG_CPU_ARCH_V5T, ARM_ARCH_V5TxM},
27300+
{TAG_CPU_ARCH_V5T, ARM_ARCH_V5T},
27301+
{TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TExP},
27302+
{TAG_CPU_ARCH_V5TE, ARM_ARCH_V5TE},
27303+
{TAG_CPU_ARCH_V5TEJ, ARM_ARCH_V5TEJ},
27304+
{TAG_CPU_ARCH_V6, ARM_ARCH_V6},
27305+
{TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6Z},
27306+
{TAG_CPU_ARCH_V6KZ, ARM_ARCH_V6KZ},
27307+
{TAG_CPU_ARCH_V6K, ARM_ARCH_V6K},
27308+
{TAG_CPU_ARCH_V6T2, ARM_ARCH_V6T2},
27309+
{TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KT2},
27310+
{TAG_CPU_ARCH_V6T2, ARM_ARCH_V6ZT2},
27311+
{TAG_CPU_ARCH_V6T2, ARM_ARCH_V6KZT2},
2731127312

2731227313
/* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
2731327314
always selected build attributes to match those of ARMv6-M
@@ -27316,25 +27317,26 @@ static const cpu_arch_ver_table cpu_arch_ver[] =
2731627317
would be selected when fully respecting chronology of architectures.
2731727318
It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
2731827319
move them before ARMv7 architectures. */
27319-
{TAG_CPU_ARCH_V6_M, ARM_ARCH_V6M},
27320-
{TAG_CPU_ARCH_V6S_M, ARM_ARCH_V6SM},
27321-
27322-
{TAG_CPU_ARCH_V7, ARM_ARCH_V7},
27323-
{TAG_CPU_ARCH_V7, ARM_ARCH_V7A},
27324-
{TAG_CPU_ARCH_V7, ARM_ARCH_V7R},
27325-
{TAG_CPU_ARCH_V7, ARM_ARCH_V7M},
27326-
{TAG_CPU_ARCH_V7, ARM_ARCH_V7VE},
27327-
{TAG_CPU_ARCH_V7E_M, ARM_ARCH_V7EM},
27328-
{TAG_CPU_ARCH_V8, ARM_ARCH_V8A},
27329-
{TAG_CPU_ARCH_V8, ARM_ARCH_V8_1A},
27330-
{TAG_CPU_ARCH_V8, ARM_ARCH_V8_2A},
27331-
{TAG_CPU_ARCH_V8, ARM_ARCH_V8_3A},
27332-
{TAG_CPU_ARCH_V8M_BASE, ARM_ARCH_V8M_BASE},
27333-
{TAG_CPU_ARCH_V8M_MAIN, ARM_ARCH_V8M_MAIN},
27334-
{TAG_CPU_ARCH_V8R, ARM_ARCH_V8R},
27335-
{TAG_CPU_ARCH_V8, ARM_ARCH_V8_4A},
27336-
{TAG_CPU_ARCH_V8, ARM_ARCH_V8_5A},
27337-
{-1, ARM_ARCH_NONE}
27320+
{TAG_CPU_ARCH_V6_M, ARM_ARCH_V6M},
27321+
{TAG_CPU_ARCH_V6S_M, ARM_ARCH_V6SM},
27322+
27323+
{TAG_CPU_ARCH_V7, ARM_ARCH_V7},
27324+
{TAG_CPU_ARCH_V7, ARM_ARCH_V7A},
27325+
{TAG_CPU_ARCH_V7, ARM_ARCH_V7R},
27326+
{TAG_CPU_ARCH_V7, ARM_ARCH_V7M},
27327+
{TAG_CPU_ARCH_V7, ARM_ARCH_V7VE},
27328+
{TAG_CPU_ARCH_V7E_M, ARM_ARCH_V7EM},
27329+
{TAG_CPU_ARCH_V8, ARM_ARCH_V8A},
27330+
{TAG_CPU_ARCH_V8, ARM_ARCH_V8_1A},
27331+
{TAG_CPU_ARCH_V8, ARM_ARCH_V8_2A},
27332+
{TAG_CPU_ARCH_V8, ARM_ARCH_V8_3A},
27333+
{TAG_CPU_ARCH_V8M_BASE, ARM_ARCH_V8M_BASE},
27334+
{TAG_CPU_ARCH_V8M_MAIN, ARM_ARCH_V8M_MAIN},
27335+
{TAG_CPU_ARCH_V8R, ARM_ARCH_V8R},
27336+
{TAG_CPU_ARCH_V8, ARM_ARCH_V8_4A},
27337+
{TAG_CPU_ARCH_V8, ARM_ARCH_V8_5A},
27338+
{TAG_CPU_ARCH_V8_1M_MAIN, ARM_ARCH_V8_1M_MAIN},
27339+
{-1, ARM_ARCH_NONE}
2733827340
};
2733927341

2734027342
/* Set an attribute if it has not already been set by the user. */
@@ -27417,7 +27419,7 @@ get_aeabi_cpu_arch_from_fset (const arm_feature_set *arch_ext_fset,
2741727419
if (ARM_FEATURE_EQUAL (*arch_ext_fset, arm_arch_any))
2741827420
{
2741927421
/* Force revisiting of decision for each new architecture. */
27420-
gas_assert (MAX_TAG_CPU_ARCH <= TAG_CPU_ARCH_V8M_MAIN);
27422+
gas_assert (MAX_TAG_CPU_ARCH <= TAG_CPU_ARCH_V8_1M_MAIN);
2742127423
*profile = 'A';
2742227424
return TAG_CPU_ARCH_V8;
2742327425
}
@@ -27688,7 +27690,7 @@ aeabi_set_public_attributes (void)
2768827690
by the base architecture.
2768927691

2769027692
For new architectures we will have to check these tests. */
27691-
gas_assert (arch <= TAG_CPU_ARCH_V8M_MAIN);
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gas_assert (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
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if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
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|| ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m))
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aeabi_set_attribute_int (Tag_DIV_use, 0);

‎gas/testsuite/gas/arm/attr-march-armv8_1-m.main.d

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# name: attributes for -march=armv8.1-m.main
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# source: blank.s
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# as: -march=armv8.1-m.main
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# readelf: -A
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# This test is only valid on EABI based ports.
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# target: *-*-*eabi* *-*-nacl*
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Attribute Section: aeabi
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File Attributes
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Tag_CPU_name: "8.1-M.MAIN"
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Tag_CPU_arch: v8.1-M.mainline
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Tag_CPU_arch_profile: Microcontroller
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Tag_THUMB_ISA_use: Yes

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