coprocessor generator

.github/workflows/ci.yml

@@ -61,7 +61,8 @@ jobs:
             cmake \
             graphviz \
             bc \
-            ghdl
+            ghdl \
+            verilator
 
       - name:
         run: |

openasip/data/ProGe/rocc_copro.sv.tmpl

@@ -96,6 +96,7 @@ module FUNAME_coprocessor
   reg [6:0]  inter_func_r;
   reg [4:0]  inter_rd_r;
   reg inter_en_r;
+  reg inter_cmd_valid;
 
   assign busy = '0; // Expects the core always accepts the data from the coprocessor
   assign cmd_ready = '1;
@@ -108,17 +109,17 @@ module FUNAME_coprocessor
 
   // CMD Control COMB
   always_comb begin
-    inter_rs1_r     <= '0;
-    inter_rs2_r     <= '0;
-    inter_opcode_r  <= '0;
-    inter_rd_r      <= '0;
-    inter_en_r      <= '0;
+    inter_rs1_r     = '0;
+    inter_rs2_r     = '0;
+    inter_opcode_r  = '0;
+    inter_rd_r      = '0;
+    inter_en_r      = '0;
       if (inter_cmd_valid == 1) begin   // Valid from the ROCC
-          inter_rs1_r     <= inter_rs1;
-          inter_rs2_r     <= inter_rs2;
-          inter_opcode_r  <= {inter_func, bits_reg, bits_reg, cmd_bits_inst_xd, cmd_bits_inst_xs1, cmd_bits_inst_xs2, bits_reg, inter_opcode};
-          inter_rd_r      <= inter_rd;
-          inter_en_r      <= '1;
+          inter_rs1_r     = inter_rs1;
+          inter_rs2_r     = inter_rs2;
+          inter_opcode_r  = {inter_func, bits_reg, bits_reg, cmd_bits_inst_xd, cmd_bits_inst_xs1, cmd_bits_inst_xs2, bits_reg, inter_opcode};
+          inter_rd_r      = inter_rd;
+          inter_en_r      = '1;
       end 
   end
 

openasip/scheduler/testbench/scheduler_tester.py

@@ -1238,7 +1238,7 @@ def printLatexHeader(self, firstColumnWidth=30, valueColumnWidth=16):
         for i in range(0, len(moreStats)*len(self.archs)):
             cols += 'l|'
 
-        sys.stdout.write('\\begin{tabular}{|l|%s} \hline\n' % cols)
+        sys.stdout.write('\\begin{tabular}{|l|%s} \\hline\n' % cols)
         sys.stdout.write(''.ljust(firstColumnWidth))
         sys.stdout.write(' & ')
         archsPrinted = 0
@@ -1272,14 +1272,14 @@ def printLatexHeader(self, firstColumnWidth=30, valueColumnWidth=16):
                 if archsPrinted < len(self.archs):
                     sys.stdout.write(' &')
 
-        sys.stdout.write('\\\\ \hline\n')
+        sys.stdout.write('\\\\ \\hline\n')
 
     def printLatexRow(self, testCase, firstColumnWidth=30):
         """
         Prints a single row of the LaTeX table.
         """
         global moreStats
-        sys.stdout.write(os.path.basename(testCase.directory).replace('_', '\_').ljust(firstColumnWidth))
+        sys.stdout.write(os.path.basename(testCase.directory).replace('_', '\\_').ljust(firstColumnWidth))
         sys.stdout.write(' & ')
 
         archsPrinted = 0

openasip/src/applibs/HWGen/FUGen.cc

@@ -460,10 +460,6 @@ FUGen::createMandatoryPorts() {
                 WireType::Vector);
         }
     }
-
-    if (addressWidth_ > 0) {
-        fu_ << IntegerConstant("addrw_c", addressWidth_);
-    }
 }
 
 void
@@ -802,10 +798,7 @@ FUGen::buildOperations() {
     }
 
     for (std::string signal : resourceInputs_) {
-        // Zero initialize this configuration to avoid simulation warnings
-        if (isLSU_ && minLatency_ < 3) {
-            operationCp << DefaultAssign(signal, "0");
-        } else if (options_.dontCareInitialization) {
+        if (options_.dontCareInitialization) {
             operationCp << DefaultAssign(signal, "-");
         } else {
             operationCp << DefaultAssign(signal, "0");
@@ -827,23 +820,6 @@ FUGen::buildOperations() {
         operationCp.reads(signal);
     }
 
-    // source -> destinations
-    std::map<std::string, std::vector<std::string>> subOpConnectionMap;
-
-    for (auto&& pair : scheduledOperations_) {
-        auto schedule = pair.second;
-        std::string name = pair.first;
-        for (auto&& operand : schedule.operands) {
-            int id = operand.id;
-            std::string source = operand.signalName;
-            std::string destination = operandSignal(name, id);
-            if (TCEString(destination).startsWith("subop") &&
-                !operand.isOutput) {
-                subOpConnectionMap[source].push_back(destination);
-            }
-        }
-    }
-
     std::set<std::string> defaultStatements;
     for (auto&& pair : scheduledOperations_) {
         auto schedule = pair.second;
@@ -904,42 +880,28 @@ FUGen::buildOperations() {
                 auto schedule = scheduledOperations_[subop];
                 std::string baseOp = schedule.baseOp;
 
-                // TODO: can we assume this?
-                auto operand = schedule.operands.front();
                 if (schedule.initialCycle == cycle) {
                     auto& impl = baseOperations_[baseOp].implementation;
                     if (!impl.empty()) {
                         std::set<std::string> statements;
                         prepareSnippet(subop, impl, onTrigger, statements);
 
-                        // TODO: A hack
-                        std::string srcSignal = "";
-                        std::vector<std::string> dstSignals;
-                        for (const auto& key : subOpConnectionMap) {
-                            if (TCEString(key.first).startsWith(subop)) {
-                                dstSignals = key.second;
-                                srcSignal = key.first;
-                                break;
-                            }
-                        }
-                        std::cerr << "subop: " << subop << " " << srcSignal
-                                  << " " << dstSignals.size() << std::endl;
-                        for (const auto& dstSignal : dstSignals) {
-                            if (operand.portWidth > operand.operandWidth) {
-                                onTrigger.append(Assign(
-                                    dstSignal,
-                                    Splice(
-                                        srcSignal, operand.operandWidth - 1,
-                                        0)));
-                            } else if (
-                                operand.portWidth < operand.operandWidth) {
-                                onTrigger.append(Assign(
-                                    dstSignal,
-                                    Ext(srcSignal, operand.operandWidth,
-                                        operand.portWidth)));
-                            } else {
-                                onTrigger.append(
-                                    Assign(dstSignal, LHSSignal(srcSignal)));
+                        for (auto&& operand : schedule.operands) {
+                            int id = operand.id;
+                            std::string srcSignal = operand.signalName;
+                            std::string dstSignal = operandSignal(subop, id);
+                            if (TCEString(dstSignal).startsWith("subop") && !operand.isOutput) {
+                                if (operand.portWidth > operand.operandWidth) {
+                                    onTrigger.append(Assign(
+                                        dstSignal,
+                                        Splice(srcSignal, operand.operandWidth - 1, 0)));
+                                } else if (operand.portWidth < operand.operandWidth) {
+                                    onTrigger.append(Assign(
+                                        dstSignal,
+                                        Ext(srcSignal, operand.operandWidth, operand.portWidth)));
+                                } else {
+                                    onTrigger.append(Assign(dstSignal, LHSSignal(srcSignal)));
+                                }
                             }
                         }
                     }
@@ -1074,9 +1036,7 @@ FUGen::buildOperations() {
         } else {
             operationCp.addVariable(SignedVariable(v.name, w));
         }
-        if (isLSU_ && minLatency_ < 3) {
-            operationCp << DefaultAssign(v.name, "0");
-        } else if (options_.dontCareInitialization) {
+        if (options_.dontCareInitialization) {
             operationCp << DefaultAssign(v.name, "-");
         } else {
             operationCp << DefaultAssign(v.name, "0");
@@ -1086,10 +1046,7 @@ FUGen::buildOperations() {
         int w = std::stoi(s.width);
         fu_ << Wire(s.name, w);     // creates the signal declaration
         operationCp.reads(s.name);  // adds it to sensitivity list
-        // Zero initialize this configuration to avoid simulation warnings
-        if (isLSU_ && minLatency_ < 3) {
-            operationCp << DefaultAssign(s.name, "0");
-        } else if (options_.dontCareInitialization) {
+        if (options_.dontCareInitialization) {
             operationCp << DefaultAssign(s.name, "-");
         } else {
             operationCp << DefaultAssign(s.name, "0");
@@ -2130,7 +2087,7 @@ FUGen::selectionlogic() {
             }
         }
         if (operations_.size() == 1) {
-            oredsignalsR = LHSSignal("config_sel");
+            oredsignalsR = LHSSignal("(config_sel)");
         }
         if (i == 1) {
             ifBlock =

openasip/src/applibs/ProGe/ProGeOptions.hh

@@ -170,9 +170,12 @@ struct ProGeOptions {
         if (coproInterface == "rocc") {
             CVXIFCoproGen = false;
             roccGen = true;
-        } else {
+        } else if (coproInterface == "cvx") {
             CVXIFCoproGen = true;
             roccGen = false;
+        } else {
+            CVXIFCoproGen = false;
+            roccGen = false;
         }
     }
 };

openasip/src/applibs/ProGe/VerilogNetlistWriter.cc

@@ -99,7 +99,7 @@ VerilogNetlistWriter::write(const std::string& dstDirectory) {
         string errorMsg = "Empty input netlist block.";
         throw InvalidData(__FILE__, __LINE__, __func__, errorMsg);
     }
-
+    formatresolve();
     writeNetlistParameterPackage(dstDirectory);
     writeBlock(block, dstDirectory);
 }
@@ -155,7 +155,7 @@ void
 VerilogNetlistWriter::writeBlock(
     const BaseNetlistBlock& block, const std::string& dstDirectory) {
     string fileName = dstDirectory + FileSystem::DIRECTORY_SEPARATOR +
-                      block.moduleName() + format_;
+                      block.moduleName() + ".v";//format_;
     if (!FileSystem::fileIsCreatable(fileName) && 
         !(FileSystem::fileExists(fileName) && 
           FileSystem::fileIsWritable(fileName))) {
@@ -779,13 +779,13 @@ VerilogNetlistWriter::parameterWidthValue(const NetlistPort& port) {
     return port.parentBlock().parameter(port.widthFormula()).value();
 }
 
-// Outputs the format as a string .v or .sv
+// Outputs the format as a string .v or .vh
 void
 VerilogNetlistWriter::formatresolve() {
     if (lang_ == SV) {
         format_ = ".sv";
     } else {
-        format_ = ".v";
+        format_ = ".vh";
     }
 }
 }

openasip/src/bintools/Compiler/riscv-tdgen/riscv-tdgen.cc

@@ -42,7 +42,7 @@ int main(int argc, char* argv[]) {
     bool rocc;
 
     // Check if the correct number of arguments is provided
-    if (argc != 5) {
+    if (!(argc == 7 || argc == 5)) {
         std::cout << "Usage: riscv-tdgen" << std::endl
                   << "   -o Output directory." << std::endl
                   << "   -a ADF path." << std::endl

testsuite/systemtest/procgen/ProGe/coprocessor_gen_test.sh

@@ -0,0 +1,43 @@
+#!/bin/bash
+### TCE TESTCASE
+### title: Test for the generation and compilation of the coprocessor files
+
+DATA=./data
+ADF="${DATA}/rv32im_test.adf"
+HDB1="${DATA}/valgen.hdb"
+OPENASIP_HDB_PATH=",../../../../openasip/hdb"
+HDB2="${OPENASIP_HDB_PATH}/generate_base32.hdb"
+HDB3="${OPENASIP_HDB_PATH}/generate_lsu_32.hdb"
+HDB4="${OPENASIP_HDB_PATH}/generate_rf_iu.hdb"
+HDB5="${OPENASIP_HDB_PATH}/asic_130nm_1.5V.hdb"
+CVX_OUT="cvx_output"
+ROCC_OUT="ROCC_output"
+
+clear_test_data() {
+    rm -rf $CVX_OUT
+    rm -rf $ROCC_OUT
+}
+
+clear_test_data
+
+generatecoprocessor -c "cvx" --hdb-list ${HDB1}${HDB2}${HDB3}${HDB4}${HDB5} -o ${CVX_OUT} $ADF \
+    >& /dev/null|| echo "Error from CV-X-IF Generation"
+
+generatecoprocessor -c "rocc" --hdb-list ${HDB1}${HDB2}${HDB3}${HDB4}${HDB5} -o ${ROCC_OUT} $ADF \
+    >& /dev/null|| echo "Error from ROCC Generation"
+
+# If verilator is found from PATH, compile and simulate
+VERILA=$(which verilator 2> /dev/null)
+if [ "x${VERILA}" != "x" ]
+then
+  cd ${ROCC_OUT}/systemverilog || exit 1
+  verilator --lint-only fu_custom.sv coprocessor_custom.sv -Wno-WIDTH >& /dev/null|| echo "ROCC compilation failed."
+
+  cd ../../${CVX_OUT}/systemverilog || exit 1
+  verilator --lint-only ../../data/cva6_config_pkg.sv cvxif_sup_pkg.sv cvxifcompressed_decoder.sv instr_tracker_custom.sv fu_custom.sv \
+  custom_coprocessor.sv ../../data/cva6_top.sv --top-module cva6_top -Wno-WIDTH -Wno-CASEINCOMPLETE -Wno-SYMRSVDWORD \
+  >& /dev/null || echo "CV-X-IF compilation failed."
+  cd ../../
+fi
+clear_test_data
+exit 0

testsuite/systemtest/procgen/ProGe/data/cva6_config_pkg.sv

@@ -0,0 +1,35 @@
+// Copyright (c) 2025  Tampere University of Technology.
+//
+// This file is part of TTA-Based Codesign Environment (TCE).
+//
+// Permission is hereby granted, free of charge, to any person obtaining a
+// copy of this software and associated documentation files (the "Software"),
+// to deal in the Software without restriction, including without limitation
+// the rights to use, copy, modify, merge, publish, distribute, sublicense,
+// and/or sell copies of the Software, and to permit persons to whom the
+// Software is furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in
+// all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+// FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+// DEALINGS IN THE SOFTWARE.
+
+package cva6_config_pkg;
+    parameter int unsigned CVA6ConfigXlen = 3;
+
+    typedef struct packed{
+        int unsigned NrScoreboardEntries;
+    } cva6_cfg_t;
+
+    localparam cva6_cfg_t cva6_cfg = '{
+        NrScoreboardEntries : unsigned'(8)
+    };
+
+
+endpackage