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Formatter: non-convergence wrapping a multi-line sum of long macros in a localparam
formatterVerilog code formatter issuesVerilog code formatter issuesStatus: Open.#2547 In chipsalliance/verible;Formatter: lexical mismatch (MacroIdentifier vs MacroIdItem) when wrapping puts a macro at end of line
formatterVerilog code formatter issuesVerilog code formatter issuesStatus: Open.#2544 In chipsalliance/verible;Verible-verilog format fails when a wrapped assign has a multiline comment
formatterVerilog code formatter issuesVerilog code formatter issuesStatus: Open.#2542 In chipsalliance/verible;Re-formatted text does not match formatted text; formatting failed to converge! Please file a bug.
formatterVerilog code formatter issuesVerilog code formatter issuesStatus: Open.#2540 In chipsalliance/verible;Verible-verilog-format fails with Check failed: leading_tokens.empty() || first_tree_token_it == ftokens.end() || first_tree_token_it->before.break_decision != SpacingOptions::kMustWrap
formatterVerilog code formatter issuesVerilog code formatter issuesStatus: Open.#2539 In chipsalliance/verible;- Status: Open.#2537 In chipsalliance/verible;
No support for SV checker construct.
rejects-valid syntaxIf the parser wrongly rejects syntactically valid code (according to SV-2017).If the parser wrongly rejects syntactically valid code (according to SV-2017).Status: Open.#2536 In chipsalliance/verible;Valid net data type declaration is rejected
rejects-valid syntaxIf the parser wrongly rejects syntactically valid code (according to SV-2017).If the parser wrongly rejects syntactically valid code (according to SV-2017).Status: Open.#2533 In chipsalliance/verible;- Status: Open.#2512 In chipsalliance/verible;
- Status: Open.#2510 In chipsalliance/verible;
The word "potential" causes false errors to show up
rejects-valid syntaxIf the parser wrongly rejects syntactically valid code (according to SV-2017).If the parser wrongly rejects syntactically valid code (according to SV-2017).Status: Open.#2504 In chipsalliance/verible;[formatter] Add option to control preprocessor indentation rules
formatterVerilog code formatter issuesVerilog code formatter issuesStatus: Open.#2503 In chipsalliance/verible;