Add tests for Crosslink devices with Interchange toolchain

Makefile

@@ -37,7 +37,7 @@ QUICKLOGIC_URL = https://storage.googleapis.com/symbiflow-arch-defs-install/quic
 
 INTERCHANGE_BASE_URL = https://storage.googleapis.com/fpga-interchange-tests/artifacts/prod/foss-fpga-tools/fpga-interchange-tests/continuous/50/20211008-072036
 INTERCHANGE_VERSION = 6ff4159
-INTERCHANGE_DEVICES ?= xc7a35t xc7a100t xc7a200t xc7z010 xczu7ev
+INTERCHANGE_DEVICES ?= xc7a35t xc7a100t xc7a200t xc7z010 xczu7ev LIFCL-17 LIFCL-40
 RAPIDWRIGHT_PATH = $(TOP_DIR)/third_party/RapidWright
 
 

assets/boards.yaml

@@ -42,10 +42,18 @@ lifcl-40:
   family: nexus
   device: LIFCL-40
   package: 9BG400C
+lifcl-40-QFN72:
+  family: nexus
+  device: LIFCL-40
+  package: QFN72
 lifcl-17:
   family: nexus
   device: LIFCL-17
   package: 8UWG72C
+lifcl-17-WLCSP72:
+  family: nexus
+  device: LIFCL-17
+  package: WLCSP72
 xczu7ev:
   family: xcup
   device: xczu7ev

assets/project/hps-accel-gen1-nexus.yaml

@@ -15,5 +15,6 @@ clock_aliases:
 vendors:
   lattice-nexus:
     - lifcl-17
+    - lifcl-17-WLCSP72
 required_toolchains:
   - nextpnr-nexus

assets/project/hps-accel-gen2-nexus.yaml

@@ -15,6 +15,7 @@ clock_aliases:
 vendors:
   lattice-nexus:
     - lifcl-17
+    - lifcl-17-WLCSP72
 required_toolchains:
   - nextpnr-nexus
 skip_toolchains:

assets/project/oneblink.yaml

@@ -16,7 +16,9 @@ vendors:
     - icebreaker
   lattice-nexus:
     - lifcl-40
+    - lifcl-40-QFN72
     - lifcl-17
+    - lifcl-17-WLCSP72
   quicklogic:
     - quickfeather
 required_toolchains:

assets/vendors.yaml

@@ -27,11 +27,14 @@ lattice-ice40:
 lattice-nexus:
   boards:
     - lifcl-40
+    - lifcl-40-QFN72
     - lifcl-17
+    - lifcl-17-WLCSP72
   toolchains:
     - nextpnr-nexus
     - synpro-radiant
     - lse-radiant
+    - nextpnr-fpga-interchange
 quicklogic:
   boards:
     - quickfeather

conf/requirements.txt

@@ -13,5 +13,5 @@ simplejson
 termcolor
 terminaltables
 yapf==0.31.0
-git+https://github.com/f4pga/edalize.git@fpga-tool-perf#egg=edalize
+git+https://github.com/antmicro/edalize.git@nexus-interchange#egg=edalize
 https://github.com/chipsalliance/f4pga/archive/de9ed1f3dba34d641c354bdb070232887254b142.zip#subdirectory=f4pga

src/hps-accel-gen1-nexus/constr/lifcl-17-WLCSP72.xdc

@@ -0,0 +1,14 @@
+set_property PACKAGE_PIN A3 [get_ports spiflash4x_cs_n]
+set_property IOSTANDARD LVCMOS18 [get_ports spiflash4x_cs_n]
+set_property PACKAGE_PIN B4 [get_ports spiflash4x_clk]
+set_property IOSTANDARD LVCMOS18 [get_ports spiflash4x_clk]
+set_property PACKAGE_PIN B5 [get_ports spiflash4x_dq[0]]
+set_property IOSTANDARD LVCMOS18 [get_ports spiflash4x_dq[0]]
+set_property PACKAGE_PIN C4 [get_ports spiflash4x_dq[1]]
+set_property IOSTANDARD LVCMOS18 [get_ports spiflash4x_dq[1]]
+set_property PACKAGE_PIN B3 [get_ports spiflash4x_dq[2]]
+set_property IOSTANDARD LVCMOS18 [get_ports spiflash4x_dq[2]]
+set_property PACKAGE_PIN B2 [get_ports spiflash4x_dq[3]]
+set_property IOSTANDARD LVCMOS18 [get_ports spiflash4x_dq[3]]
+set_property PACKAGE_PIN G3 [get_ports user_led0]
+set_property IOSTANDARD LVCMOS18H [get_ports user_led0]

src/hps-accel-gen2-nexus/constr/lifcl-17-WLCSP72.xdc

@@ -0,0 +1,22 @@
+set_property PACKAGE_PIN A3 [get_ports spiflash4x_cs_n]
+set_property IOSTANDARD LVCMOS18 [get_ports spiflash4x_cs_n]
+set_property SLEW FAST [get_ports spiflash4x_cs_n]
+set_property PACKAGE_PIN B4 [get_ports spiflash4x_clk]
+set_property IOSTANDARD LVCMOS18 [get_ports spiflash4x_clk]
+set_property SLEW FAST [get_ports spiflash4x_clk]
+set_property PACKAGE_PIN B5 [get_ports spiflash4x_dq[0]]
+set_property IOSTANDARD LVCMOS18 [get_ports spiflash4x_dq[0]]
+set_property SLEW FAST [get_ports spiflash4x_dq[0]]
+set_property PACKAGE_PIN C4 [get_ports spiflash4x_dq[1]]
+set_property IOSTANDARD LVCMOS18 [get_ports spiflash4x_dq[1]]
+set_property SLEW FAST [get_ports spiflash4x_dq[1]]
+set_property PACKAGE_PIN B3 [get_ports spiflash4x_dq[2]]
+set_property IOSTANDARD LVCMOS18 [get_ports spiflash4x_dq[2]]
+set_property SLEW FAST [get_ports spiflash4x_dq[2]]
+set_property PACKAGE_PIN B2 [get_ports spiflash4x_dq[3]]
+set_property IOSTANDARD LVCMOS18 [get_ports spiflash4x_dq[3]]
+set_property SLEW FAST [get_ports spiflash4x_dq[3]]
+set_property PACKAGE_PIN E2 [get_ports serial_rx]
+set_property IOSTANDARD LVCMOS18 [get_ports serial_rx]
+set_property PACKAGE_PIN G1 [get_ports serial_tx]
+set_property IOSTANDARD LVCMOS18H [get_ports serial_tx]

src/oneblink/constr/lifcl-17-WLCSP72.xdc

@@ -0,0 +1,7 @@
+set_property LOC B4 [get_ports clk]
+set_property LOC A3 [get_ports out]
+
+set_property IOSTANDARD LVCMOS33 [get_ports clk]
+set_property IOSTANDARD LVCMOS33 [get_ports out]
+
+create_clock -name clk -period 13.333 [get_ports clk]

src/oneblink/constr/lifcl-40-QFN72.xdc

@@ -0,0 +1,7 @@
+set_property LOC L13 [get_ports clk]
+set_property LOC G19 [get_ports out]
+
+set_property IOSTANDARD LVCMOS33 [get_ports clk]
+set_property IOSTANDARD LVCMOS33 [get_ports out]
+
+create_clock -name clk -period 13.333 [get_ports clk]

toolchains/nextpnr.py

@@ -74,7 +74,7 @@ def get_share_data(self):
         return os.path.join(nextpnr_location, '..', 'share')
 
     def configure(self):
-        assert self.xdc
+        assert self.xdc, "Interchange format requires xdc constraint file."
 
         os.makedirs(self.out_dir, exist_ok=True)
 
@@ -390,7 +390,7 @@ def __init__(self, rootdir):
 
     def prepare_edam(self):
         assert "fasm2bels" not in self.toolchain, "fasm2bels unsupported for fpga_interchange variant"
-        self.chip = self.family + self.device
+        self.chip = self.family + self.device if self.family != "nexus" else self.device
         share_dir = NextpnrGeneric.get_share_data(self)
         self.chipdb = os.path.join(
             self.rootdir, 'env', 'interchange', 'devices', self.chip,
@@ -414,10 +414,15 @@ def prepare_edam(self):
             'env.sh'
         ) + ' nextpnr fpga_interchange-' + self.device
 
-        self.yosys_synth_opts = [
-            "-flatten", "-nowidelut", "-arch {}".format(self.family), "-nodsp",
-            "-nosrl"
-        ]
+        if self.family != "nexus":
+            self.yosys_synth_opts = [
+                "-flatten", "-nowidelut", "-arch {}".format(self.family), "-nodsp",
+                "-nosrl"
+            ]
+        else:
+            self.yosys_synth_opts = [
+                "-flatten", "-nowidelut", "-nodsp"
+            ]
 
         lib_file = os.path.join(
             self.rootdir, 'env', 'interchange', 'techmaps',