Support views of ports in ChiselSim (backport #4107)

core/src/main/scala/chisel3/experimental/dataview/package.scala

@@ -261,14 +261,15 @@ package object dataview {
     * @note An Aggregate may be a view of unrelated [[Data]] (eg. like a Seq or tuple) and thus this
     *       there is no single Data representing the Target and this function will return None
     * @return The single Data target of this view or None if a single Data doesn't exist
+    * @note Returns Some(_) of the argument if it is not a view
     */
   private[chisel3] def reifySingleData(data: Data): Option[Data] = {
     val candidate: Option[Data] =
       data.topBindingOpt match {
         case None                               => None
         case Some(ViewBinding(target))          => Some(target)
         case Some(AggregateViewBinding(lookup)) => lookup.get(data)
-        case Some(_)                            => None
+        case Some(_)                            => Some(data)
       }
     candidate.flatMap { d =>
       // Candidate may itself be a view, keep tracing in those cases

src/main/scala/chisel3/simulator/package.scala

@@ -2,6 +2,7 @@ package chisel3
 
 import svsim._
 import chisel3.reflect.DataMirror
+import chisel3.experimental.dataview.reifySingleData
 import scala.collection.mutable
 import java.nio.file.{Files, Path, Paths}
 
@@ -10,7 +11,16 @@ package object simulator {
     def port(data: Data): Simulation.Port = {
       val context = Simulator.dynamicSimulationContext.value.get
       assert(context.controller == controller)
-      context.simulationPorts(data)
+      // TODO, we can support non 1-1 views, but it will require changing this API to return a Seq[Port]
+      // and packing/unpacking the BigInt literal representation.
+      val reified = reifySingleData(data).getOrElse {
+        val url = "https://github.com/chipsalliance/chisel/issues/new/choose"
+        throw new Exception(
+          s"Cannot poke $data as is a view that does not map to a single Data. " +
+            s"Please file an issue at $url requesting support for this use case."
+        )
+      }
+      context.simulationPorts(reified)
     }
   }
 

src/test/scala/chiselTests/simulator/SimulatorSpec.scala

@@ -2,6 +2,7 @@ package chiselTests.simulator
 
 import chisel3._
 import chisel3.simulator._
+import chisel3.experimental.FlatIO
 import org.scalatest.funspec.AnyFunSpec
 import org.scalatest.matchers.must.Matchers
 import org.scalatest.matchers.should.Matchers.convertToAnyShouldWrapper
@@ -132,5 +133,27 @@ class SimulatorSpec extends AnyFunSpec with Matchers {
       (actualSV should not).include("emptyBundle")
       actualSV should include("bundle_x")
     }
+
+    it("support peeking and poking FlatIO ports and other views of ports") {
+      import chisel3.experimental.dataview._
+      class SimpleModule extends Module {
+        val io = FlatIO(new Bundle {
+          val in = Input(UInt(8.W))
+          val out = Output(UInt(8.W))
+        })
+        val viewOfClock = clock.viewAs[Clock]
+        val delay = RegNext(io.in)
+        io.out := delay
+      }
+      new VerilatorSimulator("test_run_dir/simulator/flat_io_ports")
+        .simulate(new SimpleModule) { (_, dut) =>
+          import PeekPokeAPI._
+          dut.io.in.poke(12.U)
+          dut.viewOfClock.step(1)
+          dut.io.out.peek()
+          dut.io.out.expect(12)
+        }
+        .result
+    }
   }
 }