Skip to content

Commit

Permalink
[CI] Switch formatting and linting to use Ruff (#2418)
Browse files Browse the repository at this point in the history
Half of #2404.

The whole repo now has the python code format checked by `ruff format
--check` and linted by `ruff check`. _All_ python code is now subject to
these checks instead of being opt in.
  • Loading branch information
EclecticGriffin authored Feb 27, 2025
1 parent 31bbd11 commit 2d761cd
Show file tree
Hide file tree
Showing 79 changed files with 967 additions and 788 deletions.
34 changes: 6 additions & 28 deletions .github/workflows/format.yml
Original file line number Diff line number Diff line change
Expand Up @@ -39,33 +39,11 @@ jobs:
steps:
- name: Checkout
uses: actions/checkout@v4
- name: Fud Formatting check
uses: psf/black@stable
- name: Formatting check
uses: astral-sh/ruff-action@v3
with:
options: "--line-length 88 --check"
src: 'fud'
- name: Calyx-Py Formatting check
uses: psf/black@stable
args: "format --check"
- name: Linting check
uses: astral-sh/ruff-action@v3
with:
options: "--line-length 88 --check"
src: 'calyx-py'
- name: Systolic Array Formatting check
uses: psf/black@stable
with:
options: "--line-length 88 --check"
src: 'frontends/systolic-lang'
- name: Queues Formatting check
uses: psf/black@stable
with:
options: "--line-length 88 --check"
src: 'frontends/queues'
- name: Fud Linting check
uses: TrueBrain/actions-flake8@master
with:
max_line_length: 88
path: 'fud'
- name: Systolic Array Linting check
uses: TrueBrain/actions-flake8@master
with:
max_line_length: 88
path: 'frontends/systolic-lang'
args: "check"
24 changes: 12 additions & 12 deletions calyx-py/calyx/builder.py
Original file line number Diff line number Diff line change
Expand Up @@ -1101,9 +1101,9 @@ def as_control(obj):
"GroupBuilder represents continuous assignments and"
" cannot be used as a control statement"
)
assert not isinstance(
gl, ast.CombGroup
), "Cannot use combinational group as control statement"
assert not isinstance(gl, ast.CombGroup), (
"Cannot use combinational group as control statement"
)
return ast.Enable(gl.id.name)
if isinstance(obj, list):
return ast.SeqComp([as_control(o) for o in obj])
Expand Down Expand Up @@ -1162,9 +1162,9 @@ def if_with(port_comb: CellAndGroup, body, else_body=None) -> ast.If:
cond = port_comb.group
else_body = else_body or ast.Empty()

assert isinstance(
cond.group_like, ast.CombGroup
), "if condition must be a combinational group"
assert isinstance(cond.group_like, ast.CombGroup), (
"if condition must be a combinational group"
)
return ast.If(
port.expr, cond.group_like.id, as_control(body), as_control(else_body)
)
Expand All @@ -1177,9 +1177,9 @@ def while_with(port_comb: CellAndGroup, body) -> ast.While:

port = port_comb.cell.out
cond = port_comb.group
assert isinstance(
cond.group_like, ast.CombGroup
), "while condition must be a combinational group"
assert isinstance(cond.group_like, ast.CombGroup), (
"while condition must be a combinational group"
)
return ast.While(port.expr, cond.group_like.id, as_control(body))


Expand Down Expand Up @@ -1632,9 +1632,9 @@ def done(self):
"GroupLikeBuilder represents continuous assignments"
" and does not have a done hole"
)
assert not isinstance(
self.group_like, ast.CombGroup
), "done hole not available for comb group"
assert not isinstance(self.group_like, ast.CombGroup), (
"done hole not available for comb group"
)

return ExprBuilder(ast.HolePort(ast.CompVar(self.group_like.id.name), "done"))

Expand Down
6 changes: 3 additions & 3 deletions calyx-py/calyx/gen_exp.py
Original file line number Diff line number Diff line change
Expand Up @@ -484,9 +484,9 @@ def generate_exp_taylor_series_approximation(
Reference: https://en.wikipedia.org/wiki/Taylor_series#Exponential_function
"""
# TODO(cgyurgyik): Support any degree.
assert (
degree > 0 and log2(degree).is_integer()
), f"The degree: {degree} should be a power of 2."
assert degree > 0 and log2(degree).is_integer(), (
f"The degree: {degree} should be a power of 2."
)

comp = builder.component("exp")
comp.input("x", width)
Expand Down
16 changes: 8 additions & 8 deletions calyx-py/calyx/gen_ln.py
Original file line number Diff line number Diff line change
Expand Up @@ -160,10 +160,10 @@ def generate_pade_groups(comp: ComponentBuilder):
Generates groups for pade approximant componenet
"""

multiply_cells(comp, "get_x_sq", "mult_pipe", "x_reg", "x_reg"),
multiply_cells(comp, "num_term1", "n_mult_pipe1", "mult_pipe", "n1"),
multiply_cells(comp, "num_term2", "n_mult_pipe2", "x_reg", "n2"),
multiply_cells(comp, "den_term2", "d_mult_pipe2", "x_reg", "d2"),
(multiply_cells(comp, "get_x_sq", "mult_pipe", "x_reg", "x_reg"),)
(multiply_cells(comp, "num_term1", "n_mult_pipe1", "mult_pipe", "n1"),)
(multiply_cells(comp, "num_term2", "n_mult_pipe2", "x_reg", "n2"),)
(multiply_cells(comp, "den_term2", "d_mult_pipe2", "x_reg", "d2"),)

x_reg = comp.get_cell("x_reg")
add1 = comp.get_cell("add1")
Expand Down Expand Up @@ -265,7 +265,7 @@ def generate_ln(width: int, int_width: int, is_signed: bool) -> List[Component]:
comp.output("out", width)

# this is unused for some reason
and1 = comp.cell("and1", Stdlib.op("and", width, signed=False))
_and1 = comp.cell("and1", Stdlib.op("and", width, signed=False))

n = comp.reg(width, "n")
div_pipe = comp.cell(
Expand Down Expand Up @@ -298,9 +298,9 @@ def generate_ln(width: int, int_width: int, is_signed: bool) -> List[Component]:
res_reg = comp.reg(width, "res_reg")
msb = comp.comp_instance("msb", "msb_calc", check_undeclared=False)
# these 3 appear unused, not sure why
slice0 = comp.cell("slice0", Stdlib.slice(width, int_width))
rsh = comp.cell("rsh", Stdlib.op("rsh", width, is_signed))
shift_amount = comp.const("shift_amount", width, int_width)
_slice0 = comp.cell("slice0", Stdlib.slice(width, int_width))
_rsh = comp.cell("rsh", Stdlib.op("rsh", width, is_signed))
_shift_amount = comp.const("shift_amount", width, int_width)

with comp.group("get_n") as get_n:
n.write_en = HI
Expand Down
8 changes: 4 additions & 4 deletions calyx-py/calyx/numeric_types.py
Original file line number Diff line number Diff line change
Expand Up @@ -132,7 +132,7 @@ def __init__(self, value: str, width: int, is_signed: bool):

def pretty_print(self):
print(
f"""{'Signed' if self.is_signed else ''} Bitnum: {self.string_repr}
f"""{"Signed" if self.is_signed else ""} Bitnum: {self.string_repr}
------------------
Width: {self.width}
Bit String: 0b{self.bit_string_repr}
Expand Down Expand Up @@ -218,8 +218,8 @@ def __initialize_with_decimal_repr(self, value: str):
Integer width: {self.int_width}
Fractional width: {self.frac_width}
has led to overflow.
{'Required int width: {}'.format(required_int_width) if int_overflow else ''}
{'Required fractional width: {}'.format(required_frac_width) if frac_overflow else ''}
{"Required int width: {}".format(required_int_width) if int_overflow else ""}
{"Required fractional width: {}".format(required_frac_width) if frac_overflow else ""}
"""
)

Expand Down Expand Up @@ -318,7 +318,7 @@ def __negate_twos_complement(self, bitstring: str) -> str:

def pretty_print(self):
print(
f"""{'Signed' if self.is_signed else ''} Fixed Point: {self.string_repr}
f"""{"Signed" if self.is_signed else ""} Fixed Point: {self.string_repr}
------------------
Width: {self.width}, IntWidth: {self.int_width}, FracWidth: {self.frac_width}
Decimal Class: {self.decimal_repr}
Expand Down
10 changes: 5 additions & 5 deletions calyx-py/calyx/py_ast.py
Original file line number Diff line number Diff line change
Expand Up @@ -432,9 +432,9 @@ class Cell(Structure):
loc: Optional[int] = field(default_factory=PosTable.determine_source_loc)

def doc(self) -> str:
assert not (
self.is_ref and self.is_external
), "Cell cannot be both a ref and external"
assert not (self.is_ref and self.is_external), (
"Cell cannot be both a ref and external"
)
if self.is_external:
self.attributes.add(CellAttribute("external"))
if self.loc is not None:
Expand Down Expand Up @@ -1004,8 +1004,8 @@ def fixed_point_op(

@staticmethod
def pipelined_mult():
return CompInst(f"pipelined_mult", [])
return CompInst("pipelined_mult", [])

@staticmethod
def pipelined_fp_smult(width: int, int_width: int, frac_width: int):
return CompInst(f"pipelined_fp_smult", [width, int_width, frac_width])
return CompInst("pipelined_fp_smult", [width, int_width, frac_width])
2 changes: 1 addition & 1 deletion calyx-py/test/case.py
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ def add_case(prog):
my_comp = prog.component("my_comp")
comp_reg = my_comp.reg(1, "comp_reg")
in_1 = my_comp.input("in_1", 8)
out_1 = my_comp.output("out_1", 16)
_out_1 = my_comp.output("out_1", 16)

with my_comp.group("my_group") as my_group:
# Some assignments
Expand Down
6 changes: 3 additions & 3 deletions frontends/mrxl/mrxl/gen_calyx.py
Original file line number Diff line number Diff line change
Expand Up @@ -92,9 +92,9 @@ def gen_reduce_impl(
(port, cond) = cond_group(comp, idx, arr_size, f"{s_idx}")

# Perform the computation
assert (
len(stmt.binds) == 1
), "Reduce statements with multiple bind clauses are not supported"
assert len(stmt.binds) == 1, (
"Reduce statements with multiple bind clauses are not supported"
)

# Split up the accumulator and the array element
bind = stmt.binds[0]
Expand Down
6 changes: 3 additions & 3 deletions frontends/mrxl/mrxl/map.py
Original file line number Diff line number Diff line change
Expand Up @@ -71,9 +71,9 @@ def expr_to_port(expr: ast.BaseExpr):
operation = comp.add(32, f"add_{suffix}")
# ANCHOR_END: map_op

assert (
len(stmt.binds) <= 2
), "Map statements with more than 2 arguments not supported"
assert len(stmt.binds) <= 2, (
"Map statements with more than 2 arguments not supported"
)
# ANCHOR: map_inputs
with comp.group(f"eval_body_{suffix}") as evl:
# Index each array
Expand Down
3 changes: 2 additions & 1 deletion frontends/ntt-pipeline/fud/ntt.py
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
import importlib.util
from fud import errors
from fud.stages import Stage, SourceType
from fud.utils import shell
Expand All @@ -23,7 +24,7 @@ def __init__(self):
@staticmethod
def pre_install():
try:
import prettytable
importlib.util.find_spec("prettytable")
except ImportError:
raise errors.FudRegisterError(
"ntt",
Expand Down
7 changes: 4 additions & 3 deletions frontends/ntt-pipeline/gen-ntt-pipeline.py
Original file line number Diff line number Diff line change
Expand Up @@ -7,6 +7,7 @@
from calyx.utils import bits_needed
import os


def reduce_parallel_control_pass(component: ast.Component, N: int, input_size: int):
"""Reduces the amount of fan-out by reducing
parallelization in the execution flow
Expand All @@ -26,9 +27,9 @@ def reduce_parallel_control_pass(component: ast.Component, N: int, input_size: i
par { s0_r2_op_mod; s0_r3_op_mod; }
...
"""
assert (
N and 0 < N < input_size and (not (N & (N - 1)))
), f"""N: {N} should be a power of two within bounds (0, {input_size})."""
assert N and 0 < N < input_size and (not (N & (N - 1))), (
f"""N: {N} should be a power of two within bounds (0, {input_size})."""
)

reduced_controls = []
for control in component.controls.stmts:
Expand Down
4 changes: 1 addition & 3 deletions frontends/queues/evaluation/parse_pcap.py
Original file line number Diff line number Diff line change
Expand Up @@ -35,11 +35,9 @@
# python3 parse_pcap.py example.pcap example.data --start 10 --end 20 --num-flows 3

import sys
import random
import json
import dpkt
import argparse
from contextlib import nullcontext
from calyx.utils import bits_needed

CMD_PUSH = 1
Expand Down Expand Up @@ -159,7 +157,7 @@ def mac_addr(addr):
pcap = dpkt.pcap.Reader(pcap_file)

# first pass over PCAP
star_ts = None
_star_ts = None
end_ts = None
total_size = 0
make_addr_map = ADDR2INT is None
Expand Down
3 changes: 1 addition & 2 deletions frontends/queues/evaluation/plot_pcap_sim.py
Original file line number Diff line number Diff line change
@@ -1,7 +1,6 @@
import os
import sys
import json
import numpy as np
import matplotlib.pyplot as plt
from matplotlib.patches import Patch

Expand Down Expand Up @@ -83,7 +82,7 @@ def draw(packets, name):
color = pkt.color()
if pkt.punch_out is not None:
treetime = pkt.punch_out - pkt.punch_in
handle = ax.broken_barh(
_handle = ax.broken_barh(
[(pkt.punch_in, treetime)], (i, 1), facecolors=color
)

Expand Down
1 change: 0 additions & 1 deletion frontends/queues/queues/binheap/strict.py
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,6 @@
import calyx.builder as cb
from calyx.utils import bits_needed
from queues.binheap.stable_binheap import insert_stable_binheap
from queues.flow_inference import insert_boundary_flow_inference

FACTOR = 4

Expand Down
6 changes: 3 additions & 3 deletions frontends/queues/queues/queue_call.py
Original file line number Diff line number Diff line change
Expand Up @@ -32,9 +32,9 @@ def insert_runner(prog, queue, name, num_cmds, use_ranks, stats_component=None):
- 6: `component_err`, a 1-bit unsigned integer.
We raise/lower it to indicate whether an error occurred.
"""
assert (
name != "main"
), "This method is not designed for the creation of `main`-style components."
assert name != "main", (
"This method is not designed for the creation of `main`-style components."
)

runner: cb.ComponentBuilder = prog.component(name)

Expand Down
6 changes: 1 addition & 5 deletions frontends/queues/queues/strict_or_rr.py
Original file line number Diff line number Diff line change
Expand Up @@ -2,8 +2,6 @@
import calyx.builder as cb
import calyx.py_ast as ast
from calyx.utils import bits_needed
import queues.fifo as fifo
import queues.flow_inference as fi

# This determines the maximum possible length of the queue:
# The max length of the queue will be 2^QUEUE_LEN_FACTOR.
Expand Down Expand Up @@ -141,9 +139,7 @@ def insert_queue(
),
len_decr,
(
pifo.reg_store(hot, og_hot.out)
if not is_round_robin
else ast.Empty
pifo.reg_store(hot, og_hot.out) if not is_round_robin else ast.Empty
# If we are not generating a round-robin PIFO,
# we are generating a strict PIFO.
# We need to restore `hot` to its original value.
Expand Down
1 change: 0 additions & 1 deletion frontends/queues/queues/tree.py
Original file line number Diff line number Diff line change
@@ -1,6 +1,5 @@
# pylint: disable=import-error
import calyx.builder as cb
from calyx.utils import bits_needed


def insert_tree(prog, name, root, children, flow_infer):
Expand Down
6 changes: 3 additions & 3 deletions frontends/queues/test_data_gen/gen_oracle_data.py
Original file line number Diff line number Diff line change
Expand Up @@ -59,9 +59,9 @@ def no_err_cmds_list(queue_size, num_cmds):
commands += (num_cmds - len(commands)) * [0]
# The above command will add either zero or one `pop` commands to the end.

assert (
len(commands) == num_cmds
), f"Length of commands list was {len(commands)}, expected {num_cmds}"
assert len(commands) == num_cmds, (
f"Length of commands list was {len(commands)}, expected {num_cmds}"
)
return commands


Expand Down
10 changes: 5 additions & 5 deletions frontends/queues/test_data_gen/queues.py
Original file line number Diff line number Diff line change
Expand Up @@ -209,14 +209,14 @@ def is_ripe(self, element, time):
"""Check that an element is 'ripe' - i.e. its ready time has passed"""
return element["time"] <= time

def binsert(self, val, time, rank, l, r):
def binsert(self, val, time, rank, left, r):
"""Inserts element into list such that rank ordering is preserved
Uses variant of binary search algorithm.
"""
if l == r:
return self.data.insert(l, {"val": val, "time": time, "rank": rank})
if left == r:
return self.data.insert(left, {"val": val, "time": time, "rank": rank})

mid = (l + r) // 2
mid = (left + r) // 2

if rank == self.data[mid]["rank"]:
return self.data.insert(mid, {"val": val, "time": time, "rank": rank})
Expand All @@ -225,7 +225,7 @@ def binsert(self, val, time, rank, l, r):
return self.binsert(val, time, rank, mid + 1, r)

if rank < self.data[mid]["rank"]:
return self.binsert(val, time, rank, l, mid)
return self.binsert(val, time, rank, left, mid)

def push(self, val, rank=0, time=0, insertion_count=None) -> None:
"""Pushes to a PIEO.
Expand Down
Loading

0 comments on commit 2d761cd

Please sign in to comment.