Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Add support for SIMD Exceptions reporting and new x86 ISAs #108

Merged
merged 3 commits into from
Nov 7, 2024
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension


Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
7 changes: 7 additions & 0 deletions CHANGELOG.md
Original file line number Diff line number Diff line change
Expand Up @@ -5,6 +5,13 @@ All notable (user-facing) changes to this project will be documented in this fil
The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/).


## [2.3.0] - 2024-11-07

### Added
- Support for SIMD Exceptions reporting (for instructions that generate SIMD exceptions; this is equivalent to also setting or testing the associated bits in the `MXCSR`).
- Support for the following new x86 ISAs: MOVRS, MSR_IMM, AMX-FP8, AMX-TRANSPOSE, AMX-TF32, AMX-AVX512, AMX-MOVRS and EVEX-encoded SM4 instructions.


## [2.2.0] - 2024-09-16

### Added
Expand Down
13 changes: 9 additions & 4 deletions bddisasm/bdx86_decoder.c
Original file line number Diff line number Diff line change
Expand Up @@ -4297,7 +4297,8 @@ NdVexExceptionChecks(
}

// Handle AMX exception class.
if (Instrux->ExceptionType == ND_EXT_AMX_E4)
if (Instrux->ExceptionType == ND_EXT_AMX_E4 ||
Instrux->ExceptionType == ND_EXT_AMX_E10)
{
// #UD if srcdest == src1, srcdest == src2 or src1 == src2. All three operands are tile regs.
if (Instrux->Operands[0].Info.Register.Reg == Instrux->Operands[1].Info.Register.Reg ||
Expand Down Expand Up @@ -4374,7 +4375,8 @@ NdCopyInstructionInfo(
Instrux->ValidModes.Raw = Idbe->ValidModes;
Instrux->ValidPrefixes.Raw = Idbe->ValidPrefixes;
Instrux->ValidDecorators.Raw = Idbe->ValidDecorators;
*((ND_UINT8*)&Instrux->FpuFlagsAccess) = Idbe->FpuFlags;
Instrux->FpuFlagsAccess.Raw = Idbe->FpuFlags;
Instrux->SimdExceptions.Raw = Idbe->SimdExc;
// Valid for EVEX, VEX and SSE instructions only. A value of 0 means it's not used.
Instrux->ExceptionType = Idbe->ExcType;
Instrux->TupleType = Idbe->TupleType;
Expand Down Expand Up @@ -4465,8 +4467,11 @@ NdDecodeWithContext(
return ND_STATUS_INVALID_PARAMETER;
}

// Initialize with zero.
nd_memzero(Instrux, sizeof(INSTRUX));
if (0 == (Context->Options & ND_OPTION_SKIP_ZERO_INSTRUX))
{
// Initialize with zero.
nd_memzero(Instrux, sizeof(INSTRUX));
}

Instrux->DefCode = (ND_UINT8)Context->DefCode;
Instrux->DefData = (ND_UINT8)Context->DefData;
Expand Down
Loading
Loading