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ref(riscv): refactor vimsic interrupt injection #310

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17 changes: 0 additions & 17 deletions src/arch/riscv/irqc/aia/imsic.c
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Original file line number Diff line number Diff line change
Expand Up @@ -67,23 +67,6 @@ void imsic_clr_pend(irqid_t intp_id)
csrs_sireg_clear(1UL << imsic_eie_bit(intp_id));
}

/**
* For now we only support 1 guest file per hart.
* Should I remove the guest_file from the API?
*/
void imsic_inject_pend(size_t guest_file, irqid_t intp_id)
{
UNUSED_ARG(guest_file);

csrs_vsiselect_write(IMSIC_EIP + imsic_eie_index(intp_id));
csrs_vsireg_clear(1UL << imsic_eie_bit(intp_id));
}

void imsic_send_msi(cpuid_t target_cpu)
{
imsic[target_cpu]->s_file.seteipnum_le = interrupts_ipi_id;
}

void imsic_handle(void)
{
/* Read STOPEI and write to it to claim the interrupt */
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23 changes: 18 additions & 5 deletions src/arch/riscv/irqc/aia/inc/imsic.h
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Original file line number Diff line number Diff line change
Expand Up @@ -28,8 +28,11 @@ struct imsic_intp_file_hw {

struct imsic_global_hw {
struct imsic_intp_file_hw s_file;
struct imsic_intp_file_hw guest_file;
} __attribute__((__packed__, aligned(0x1000ULL)));

extern volatile struct imsic_global_hw* imsic[PLAT_CPU_NUM];

/**
* @brief Initializes the IMSIC
*
Expand Down Expand Up @@ -72,15 +75,25 @@ void imsic_set_enbl(irqid_t intp_id);
*
* @param target_cpu The ID of the target CPU
*/
void imsic_send_msi(cpuid_t target_cpu);
static inline void imsic_send_msi(cpuid_t target_cpu, irqid_t msi_id)
{
imsic[target_cpu]->s_file.seteipnum_le = msi_id;
}

/**
* @brief Inject an interrupt into a guest.
* @brief Sends an MSI to the guest file specified CPU with the specified IPI ID.
*
* The function sends an MSI to the guest file specified CPU by setting the seteipnum_le
* register in the IMSIC. The seteipnum_le register is used to specify the ID of the
* interrupt being sent. Only little endian is supported. This function assume a single guest
* interrupt file per hart.
*
* @param guest_file Guest interrupt file ID
* @param intp_id Interrupt ID
* @param target_cpu The ID of the target CPU
*/
void imsic_inject_pend(size_t guest_file, irqid_t intp_id);
static inline void imsic_send_guest_msi(cpuid_t target_cpu, irqid_t msi_id)
{
imsic[target_cpu]->guest_file.seteipnum_le = msi_id;
}

/**
* @brief Handles interrupts in the IMSIC.
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3 changes: 2 additions & 1 deletion src/arch/riscv/irqc/aia/inc/irqc.h
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Expand Up @@ -91,7 +91,8 @@ static inline irqid_t irqc_reserve(irqid_t pintp_id)

static inline void irqc_send_ipi(cpuid_t target_cpu)
{
imsic_send_msi(target_cpu);
extern irqid_t interrupts_ipi_id;
imsic_send_msi(target_cpu, interrupts_ipi_id);
}

static inline void irqc_handle(void)
Expand Down
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