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Releasing version 2.0.6 (#702)
* Releasing CL_SDE software example to demonstrate how to use the Streaming Data Engine (SDE) DMA on small shell. * Fixing the virtual ethernet PacketGen Dual Instance Loopback example to forward packets back to the PacketGen instance. * Fixing DDR backdoor access in simulation.
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‎ERRATA.md

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6. Simulation of the [HBM monitor interface](./hdk/docs/AWS_Shell_Interface_Specification.md/#hbm-monitor-interface) is not supported in this release. The HBM IP always passes initialization and remains in an operating state for all tests. Simulation support for the HBM monitor will be added in a future release.
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7. AFIs created based on HDK XDMA shell or Vitis are not supported on F2
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instances at this time.
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8. The following ddr simulation backdoor test is not working with 64GB memory:
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- test_ddr_peek_bdr_walking_ones
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7. AFIs created based on HDK XDMA shell or Vitis are not supported on F2 instances at this time.
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## SDK
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‎README.md

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![f2_headline_graphic](./shared/assets/f2_headline_graphic.png)
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# AWS F2
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## F2 FPGA Development Kit Overview
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**Note**: The documentation and assets provided on this branch (and other branches prefixed with `f2`) are relevant to F2 instance type development only. F2 is the successor to F1. For F1 development, refer to [this branch](https://github.com/aws/aws-fpga/tree/master).
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The documentation and assets provided on this branch (and other branches prefixed with `f2`) are relevant to F2 instances only.
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The F2 FPGA Development Kit is a hardware-software development kit that enables developers to create accelerators for the high-performance accelerator cards on EC2 F2 instances. Using the development kit, you can architect, simulate, optimize, and test your designs.
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We are currently migrating our F2 documentation to comply with the ReadTheDocs standard. To familiarize yourself with the new layout, please [click here](https://awsdocs-fpga-f2.readthedocs-hosted.com).
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## Support
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# ❗Amazon EC2 F1 End of Life Notice❗
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We are retiring the F1 instances on December 20, 2025.
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Only existing F1 customers who have run F1 instances anytime between Dec 2023 - Dec 2024 can restart or launch new F1 instances. Effective December 20, 2025, F1 instances or access data stored on F1 instance local storage will be no longer available. Please transfer any needed data stored in F1 instance local storage before December 20, 2025.
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| aws-fpga F1 Branch | devKit Version | devAMI |
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|:-------------------------|:---------------|:----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------|
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| [f1_xdma_shell](https://github.com/aws/aws-fpga/tree/f1_xdma_shell) | 1.4.25+ | [FPGA Developer AMI 1.16.1 (Ubuntu)](https://aws.amazon.com/marketplace/pp/prodview-f5kjsenkfkz5u) |
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| [f1_small_shell](https://github.com/aws/aws-fpga/tree/f1_small_shell) | 1.4.25+ | [FPGA Developer AMI 1.16.1 (Ubuntu)](https://aws.amazon.com/marketplace/pp/prodview-f5kjsenkfkz5u) |
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# Support
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For any issues with this developer kit documentation or code, please open a [GitHub issue](https://github.com/aws/aws-fpga/issues) with all steps to reproduce.
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To raise an issue or receive support, please [open an issue on the official GitHub page](https://github.com/aws/aws-fpga/issues).
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For questions, please open a [re:Post issue with the 'FPGA Development' tag](https://repost.aws/tags/TAc7ofO5tbQRO57aX1lBYbjA/fpga-development).

‎RELEASE_NOTES.md

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# F2 Developer Kit Release Notes
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## v2.0.6
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* Releasing [CL_SDE software examples](./hdk/cl/examples/cl_sde/software/src/README.md) to demonstrate how to use the [Streaming Data Engine (SDE)](./sdk/apps/virtual-ethernet/doc/SDE_HW_Guide.md) DMA on [small shell](./User_Guide_AWS_EC2_FPGA_Development_Kit.md#aws-shells).
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* Fixing the [virtual ethernet](./sdk/apps/virtual-ethernet/doc/Virtual_Ethernet_Application_Guide.md#packetgen-dual-instance-loopback) PacketGen Dual Instance Loopback example to forward packets back to the PacketGen instance.
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* Fixing DDR backdoor access in simulation.
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## v2.0.5
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* Releasing instructions for using the Vivado GUI.

‎docs-rtd/Makefile

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"results in $(BUILDDIR)/doctest/output.txt."
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spelling:
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$(SPHINXBUILD) -b spelling source/ build/
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$(SPHINXBUILD) -b spelling source/ build/
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links:
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make clean && make html && python3 ../shared/bin/check_doc_links.py

‎docs-rtd/source/ERRATA.rst

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Shell Errata
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------------
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Shell errata is `documented here <./hdk/docs/AWS_Shell_ERRATA.html>`__
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Shell errata is `documented here <./hdk/docs/AWS-Shell-ERRATA.html>`__
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HDK
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---
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CL builds using the XDMA Shell will result in a build failure.
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3. CL simulation might show the following "error" message if the `CL
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clock generator <./hdk/docs/AWS_CLK_GEN_spec.html>`__ is contained in
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clock generator <./hdk/docs/AWS-CLK-GEN-spec.html>`__ is contained in
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the design. By default, the generator blocks all output clocks
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(except for ``o_clk_main_a0``) and asserts all output resets. This
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behavior violates the built-in reset check in the `AXI SmartConnect
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6. Simulation of the `HBM monitor
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interface <./hdk/docs/AWS_Shell_Interface_Specification.html#hbm-monitor-interface>`__
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interface <./hdk/docs/AWS-Shell-Interface-Specification.html#hbm-monitor-interface>`__
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is not supported in this release. The HBM IP always passes
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initialization and remains in an operating state for all tests.
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7. AFIs created based on HDK XDMA shell or Vitis are not supported on F2
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8. The following ddr simulation backdoor test is not working with 64GB memory:
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SDK
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3. Support for Vitis software emulation has been deprecated by AMD, therefore, no longer supported.
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`Back to Home <./index.html>`__
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`Back to Home <./home.html>`__

‎docs-rtd/source/RELEASE_NOTES.rst renamed to ‎docs-rtd/source/RELEASE-NOTES.rst

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F2 Developer Kit Release Notes
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==============================
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.. _v206:
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v2.0.6
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------
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- Releasing `CL_SDE software examples <./hdk/cl/examples/cl-sde/software/src/README.html>`__ to demonstrate how to use the `Streaming Data Engine (SDE) <./sdk/apps/virtual-ethernet/doc/Virtual-Ethernet-Application-Guide.html>`__ DMA for `small shell <./User-Guide-AWS-EC2-FPGA-Development-Kit.html#aws-shells>`__.
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- Fixing the `virtual ethernet <./sdk/apps/virtual-ethernet/doc/SDE-HW-Guide.html>`__ PacketGen Dual Instance Loopback example to forward packets back to the PacketGen instance.
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- Fixing DDR backdoor access in simulation.
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.. _v205:
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v2.0.5
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------
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- Releasing instructions for using the Vivado GUI.
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- Updating virtual_ethernet_install.py to no longer require sudo when run.
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- Updating f2_mgmt_example, load_multiple_fpga.c, to load AFIs in parallel.
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- Updated ReadTheDocs theme.
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- Added the "F2 Software Performance Optimization Guide" with techniques for f2.48xlarge instances
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v2.0.4
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Initial release. F2 general-availability companion.
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`Back to Home <./index.html>`__
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`Back to Home <./home.html>`__

‎docs-rtd/source/User_Guide_AWS_EC2_FPGA_Development_Kit.rst renamed to ‎docs-rtd/source/User-Guide-AWS-EC2-FPGA-Development-Kit.rst

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On-premise environment: Customers can set up a on-premise development
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environment using 2024.1 AMD tools with their own licenses. Refer to
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this guide `here <./hdk/docs/on-premise-licensing-help.html>`__ for
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.. _aws-shells:
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The HDK design flow currently supports the Small Shell. The Small Shell
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offers 88% usable FPGA resources. The `common
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interface <./hdk/docs/AWS-Shell-Interface-Specification.html>`__ (is
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`cl_ports.vh <https://github.com/aws/aws-fpga/blob/f2/hdk/common/shell_stable/design/interfaces/cl_ports.vh>`__)
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along with the `floorplans <./hdk/docs/shell_floorplan.html>`__ and
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along with the `floorplans <./hdk/docs/shell-floorplan.html>`__ and
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simulations <./hdk/docs/RTL-Simulation-Guide-for-HDK-Design-Flow.html>`__
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interfaces <./hdk/docs/AWS-Shell-Interface-Specification.html>`__, e.g. `the HBM monitor
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interface <./hdk/docs/AWS-Shell-Interface-Specification.html#hbm-monitor-interface>`__
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floorplan <./hdk/docs/shell-floorplan.html>`__ and locations of major
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- Deep dive into `CL examples <./hdk/README.html#cl-examples>`__ to
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`CL_TEMPLATE <./hdk/cl/examples/CL-TEMPLATE/README.html>`__ example.
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- Connect to a custom CL design in FPGA through `Virtual
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JTAG <./hdk/docs/Virtual-JTAG-XVC.html>`__ to run hardware debug.
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.. |f2_instances| image:: ./_static/instance_sizes_20250110.png
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.. |image1| image:: ./_static/accel_card_specs_20250110.png
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`Back to Home <./index.html>`__
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`Back to Home <./home.html>`__

‎docs-rtd/source/_templates/layout.html

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{% extends "!layout.html" %}
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‎docs-rtd/source/all_links.rst renamed to ‎docs-rtd/source/all-links.rst

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hdk/cl/examples/cl-dram-hbm-dma/verif/README
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cl_mem_perf
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cl_sde
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hdk/cl/examples/cl-sde/verif/README
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hdk/cl/examples/CL-TEMPLATE/README
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General Documentation
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hdk/docs/AWS-Fpga-Pcie-Memory-Map
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hdk/docs/AWS-Shell-ERRATA
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hdk/docs/AWS-Shell-Interface-Specification
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hdk/docs/Clock-Recipes-User-Guide
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hdk/docs/on-premise-licensing-help
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hdk/docs/RTL-Simulation-Guide-for-HDK-Design-Flow
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hdk/docs/Supported-DDR-Modes
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RELEASE-NOTES
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`Back to Home <./index.html>`__
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`Back to Home <./home.html>`__

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