ERRATA: Add AMD HBM IP bug (#699)

Author: czfpga

ERRATA.md

@@ -7,15 +7,21 @@ Shell errata is [documented here](./hdk/docs/AWS_Shell_ERRATA.md)
 
 ## HDK
 
-1. Support for the XDMA Shell in the HDK design flow is not available at this time. CL builds using the XDMA Shell will result in a build failure.
+1. Address Aliasing Bug in AMD HBM IP with Customer Address Mapping
 
-2. CL simulation might show the following "error" message if the [CL clock generator](./hdk/docs/AWS_CLK_GEN_spec.md) is contained in the design. By default, the generator blocks all output clocks (except for `o_clk_main_a0`) and asserts all output resets. This behavior violates the built-in reset check in the [AXI SmartConnect IP](https://www.xilinx.com/products/intellectual-property/smartconnect.html#overview). This message can be safely ignored. A Fix for this issue is in progress.
+   * An address aliasing bug has been identified in AMD HBM IP when the IP's "Customer Address Map" option is enabled for a 16GB HBM implementation. The bug allows a single memory entry to be accessed via two different addresses, which might lead to data corruption. More information about this bug will be published by AMD in the Ultrascale+ product errata.
+
+   * For now, customers using 16GB HBM implementation should disable the "Customer Address Map" option in the IP until a fix is released by AMD.
+
+2. Support for the XDMA Shell in the HDK design flow is not available at this time. CL builds using the XDMA Shell will result in a build failure.
+
+3. CL simulation might show the following "error" message if the [CL clock generator](./hdk/docs/AWS_CLK_GEN_spec.md) is contained in the design. By default, the generator blocks all output clocks (except for `o_clk_main_a0`) and asserts all output resets. This behavior violates the built-in reset check in the [AXI SmartConnect IP](https://www.xilinx.com/products/intellectual-property/smartconnect.html#overview). This message can be safely ignored. A Fix for this issue is in progress.
 
     ```bash
     # ** Error: [SmartConnect 500-33] s_sc_aresetn should be asserted for at least 16 cycles of m_sc_aclk. tb.card.fpga.CL.CL_HBM.HBM_PRESENT_EQ_1.AXI_CONVERTER_AXI4_AXI3.cl_axi_sc_1x1_i.smartconnect_0.inst.s00_nodes.s00_aw_node.inst.<protected>.<protected>
     ```
 
-3. CL simulation might show the following "error" message. This message can be safely ignored. A Fix for this issue is in progress.
+4. CL simulation might show the following "error" message. This message can be safely ignored. A Fix for this issue is in progress.
 
     ```bash
     # Initializing memory from data in 'ddr4_ddr_10.mem'.
@@ -24,14 +30,15 @@ Shell errata is [documented here](./hdk/docs/AWS_Shell_ERRATA.md)
     #   ERROR: Failed to write data burst length to 16. Only <4,8> are valid.
     ```
 
-4. XSIM simulator does not support a cycle-accurate simulation model for the HBM IP. We’re observing significantly longer simulation times compared to VCS and Questa simulators. This is caused by the HBM BFM used in XSIM. Therefore, running HBM simulation using VCS or Questa is strongly recommended.
+5. XSIM simulator does not support a cycle-accurate simulation model for the HBM IP. We’re observing significantly longer simulation times compared to VCS and Questa simulators. This is caused by the HBM BFM used in XSIM. Therefore, running HBM simulation using VCS or Questa is strongly recommended.
 
-5. Simulation of the [HBM monitor interface](./hdk/docs/AWS_Shell_Interface_Specification.md/#hbm-monitor-interface) is not supported in this release. The HBM IP always passes initialization and remains in an operating state for all tests. Simulation support for the HBM monitor will be added in a future release.
+6. Simulation of the [HBM monitor interface](./hdk/docs/AWS_Shell_Interface_Specification.md/#hbm-monitor-interface) is not supported in this release. The HBM IP always passes initialization and remains in an operating state for all tests. Simulation support for the HBM monitor will be added in a future release.
 
-6. AFIs created based on HDK XDMA shell or Vitis are not supported on F2
+7. AFIs created based on HDK XDMA shell or Vitis are not supported on F2
    instances at this time.
 
-7. The following ddr simulation backdoor test is not working with 64GB memory:
+8. The following ddr simulation backdoor test is not working with 64GB memory:
+
    - test_ddr_peek_bdr_walking_ones
 
 ## SDK

docs-rtd/source/ERRATA.rst

@@ -9,10 +9,22 @@ Shell errata is `documented here <./hdk/docs/AWS_Shell_ERRATA.html>`__
 HDK
 ---
 
-1. Support for the XDMA Shell in the HDK design flow is not available at this time.
+
+1. Address Aliasing Bug in AMD HBM IP with Customer Address Mapping
+
+   An address aliasing bug has been identified in AMD HBM IP when the IP's
+   "Customer Address Map" option is enabled for a 16GB HBM implementation. The
+   bug allows a single memory entry to be accessed via two different addresses,
+   which might lead to data corruption. More information about this bug will be
+   published by AMD in the Ultrascale+ production errata.
+
+   For now, customers using 16GB HBM implementation should disable the
+   "Customer Address Map" option in the IP until a fix is released by AMD.
+
+2. Support for the XDMA Shell in the HDK design flow is not available at this time.
    CL builds using the XDMA Shell will result in a build failure.
 
-2. CL simulation might show the following "error" message if the `CL
+3. CL simulation might show the following "error" message if the `CL
    clock generator <./hdk/docs/AWS_CLK_GEN_spec.html>`__ is contained in
    the design. By default, the generator blocks all output clocks
    (except for ``o_clk_main_a0``) and asserts all output resets. This
@@ -25,7 +37,7 @@ HDK
 
       # ** Error: [SmartConnect 500-33] s_sc_aresetn should be asserted for at least 16 cycles of m_sc_aclk. tb.card.fpga.CL.CL_HBM.HBM_PRESENT_EQ_1.AXI_CONVERTER_AXI4_AXI3.cl_axi_sc_1x1_i.smartconnect_0.inst.s00_nodes.s00_aw_node.inst.<protected>.<protected>
 
-3. CL simulation might show the following "error" message. This message
+4. CL simulation might show the following "error" message. This message
    can be safely ignored. A Fix for this issue is in progress.
 
    .. code:: bash
@@ -35,23 +47,23 @@ HDK
       #   'ddr4_ddr_10.mem' set write data width to x4.
       #   ERROR: Failed to write data burst length to 16. Only <4,8> are valid.
 
-4. XSIM simulator does not support a cycle-accurate simulation model for
+5. XSIM simulator does not support a cycle-accurate simulation model for
    the HBM IP. We’re observing significantly longer simulation times
    compared to VCS and Questa simulators. This is caused by the HBM BFM
    used in XSIM. Therefore, running HBM simulation using VCS or Questa
    is strongly recommended.
 
-5. Simulation of the `HBM monitor
+6. Simulation of the `HBM monitor
    interface <./hdk/docs/AWS_Shell_Interface_Specification.html#hbm-monitor-interface>`__
    is not supported in this release. The HBM IP always passes
    initialization and remains in an operating state for all tests.
    Simulation support for the HBM monitor will be added in a future
    release.
 
-6. AFIs created based on HDK XDMA shell or Vitis are not supported on F2
+7. AFIs created based on HDK XDMA shell or Vitis are not supported on F2
    instances at this time.
 
-7. The following ddr simulation backdoor test is not working with 64GB memory:
+8. The following ddr simulation backdoor test is not working with 64GB memory:
 
    - test_ddr_peek_bdr_walking_ones
 
@@ -69,4 +81,4 @@ Software defined Accelerator Development (Vitis)
 
 3. Support for Vitis software emulation has been deprecated by AMD, therefore, no longer supported.
 
-`Back to Home <./index.html>`__
+`Back to Home <./index.html>`__