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Release 2.0.5
* Releasing instructions for using the Vivado GUI. * Updating virtual_ethernet_install.py to no longer require sudo when run. * Updating f2_mgmt_example, load_multiple_fpga.c, to load AFIs in parallel. * Updated ReadTheDocs theme. * Added the "F2 Software Performance Optimization Guide" with techniques for f2.48xlarge instances
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‎RELEASE_NOTES.md

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# F2 Developer Kit Release Notes
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## v2.0.5
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* Releasing instructions for using the Vivado GUI.
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* Updating virtual_ethernet_install.py to no longer require sudo when run.
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* Updating f2_mgmt_example, load_multiple_fpga.c, to load AFIs in parallel.
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* Updated ReadTheDocs theme.
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* Added the "F2 Software Performance Optimization Guide" with techniques for f2.48xlarge instances
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## v2.0.4
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* Release of new F2 instance size, **f2.6xlarge**:

‎docs-rtd/requirements.txt

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sphinx==5.3.0
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sphinx>=6.1.0
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pyenchant==3.2.2
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termcolor==2.5.0
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sphinxcontrib-spelling==8.0.1
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sphinxcontrib-spelling==8.0.1
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sphinx_book_theme>=1.1.3
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requests==2.32.3

‎docs-rtd/source/ERRATA.rst

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SDK
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---
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* N/A
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Software defined Accelerator Development (Vitis)
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------------------------------------------------
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2. Support for Vitis 2024.1 accelerator binary creation and AFI creation is not supported, but will be released at a later time.
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3. Support for Vitis software emulation has been deprecated by AMD, therefore, no longer supported.
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`Back to Home <./index.html>`__

‎docs-rtd/source/RELEASE_NOTES.rst

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------
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Initial release. F2 general-availability companion.
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`Back to Home <./index.html>`__

‎docs-rtd/source/User_Guide_AWS_EC2_FPGA_Development_Kit.rst

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`AWS EC2 FPGA Development Kit <https://github.com/aws/aws-fpga>`__
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==================================================================
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`AWS EC2 FPGA Development Kit User Guide <https://github.com/aws/aws-fpga>`__
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=============================================================================
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The development kit includes example designs to get you familiar with
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developing for AWS EC2 FPGA Instances.
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.. |f2_instances| image:: ./_static/instance_sizes_20250110.png
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.. |image1| image:: ./_static/accel_card_specs_20250110.png
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.. |f2_f1_comp| image:: ./_static/f2_f1_comp_20250110.png
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`Back to Home <./index.html>`__

‎docs-rtd/source/all_links.rst

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All Documents by Section
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========================
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.. toctree::
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:maxdepth: 1
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User_Guide_AWS_EC2_FPGA_Development_Kit
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HDK
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---
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.. toctree::
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:maxdepth: 1
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hdk/README
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Custom Logic Examples
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^^^^^^^^^^^^^^^^^^^^^
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.. toctree::
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:maxdepth: 1
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hdk/cl/CHECKLIST_BEFORE_BUILDING_CL
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cl_dram_hbm_dma
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"""""""""""""""
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.. toctree::
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:maxdepth: 1
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hdk/cl/examples/cl_dram_hbm_dma/README
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hdk/cl/examples/cl_dram_hbm_dma/verif/README
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cl_mem_perf
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"""""""""""
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.. toctree::
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:maxdepth: 1
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hdk/cl/examples/cl_mem_perf/README
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hdk/cl/examples/cl_mem_perf/verif/README
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cl_sde
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""""""
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.. toctree::
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:maxdepth: 1
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hdk/cl/examples/cl_sde/README
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hdk/cl/examples/cl_sde/verif/README
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CL_TEMPLATE
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"""""""""""
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.. toctree::
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:maxdepth: 1
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hdk/cl/examples/CL_TEMPLATE/README
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General Documentation
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^^^^^^^^^^^^^^^^^^^^^
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.. toctree::
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:maxdepth: 1
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hdk/docs/AWS_CLK_GEN_spec
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hdk/docs/AWS_Fpga_Pcie_Memory_Map
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hdk/docs/AWS_Shell_ERRATA
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hdk/docs/AWS_Shell_Interface_Specification
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hdk/docs/Clock_Recipes_User_Guide
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hdk/docs/on_premise_licensing_help
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hdk/docs/RTL_Simulation_Guide_for_HDK_Design_Flow
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hdk/docs/shell_floorplan
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hdk/docs/Supported_DDR_Modes
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hdk/docs/Virtual_JTAG_XVC
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SDK
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---
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.. toctree::
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:maxdepth: 1
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sdk/README
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FPGA Management
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^^^^^^^^^^^^^^^
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.. toctree::
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:maxdepth: 1
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sdk/userspace/fpga_mgmt_examples/README
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sdk/userspace/fpga_mgmt_tools/README
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Virtual Ethernet
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^^^^^^^^^^^^^^^^
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.. toctree::
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:maxdepth: 1
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sdk/apps/virtual-ethernet/README
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sdk/apps/virtual-ethernet/doc/SDE_HW_Guide
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sdk/apps/virtual-ethernet/doc/Virtual_Ethernet_Application_Guide
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Vitis
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-----
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.. toctree::
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:maxdepth: 1
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vitis/README
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Release Notes and Errata
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------------------------
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.. toctree::
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:maxdepth: 1
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RELEASE_NOTES
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ERRATA
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`Back to Home <./index.html>`__

‎docs-rtd/source/conf.py

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'sphinx.ext.imgmath',
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'sphinx.ext.extlinks',
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'sphinxcontrib.spelling',
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'sphinx_book_theme'
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]
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# Makes the spelling filters visible.
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#modindex_common_prefix = []
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# Relative path definitions
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build_hdk_to_repo_root: str = "../../../.."
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build_hdk_to_hdk_root: str = f"{build_hdk_to_repo_root}/hdk"
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build_hdk_to_cl_examples_root: str = f"{build_hdk_to_hdk_root}/cl/examples"
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build_hdk_to_cl_template_build_scripts: str = f"{build_hdk_to_cl_examples_root}/CL_TEMPLATE/build/scripts"
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build_hdk_to_cl_template_build_constraints: str = f"{build_hdk_to_cl_examples_root}/CL_TEMPLATE/build/constraints"
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build_hdk_to_hdk_common_shell_stable_build_scripts: str = f"{build_hdk_to_hdk_root}/common/shell_stable/build/scripts"
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build_docs: str = "docs"
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build_cl_examples: str = "cl/examples"
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cl_dram_readme: str = "cl_dram_hbm_dma/README.html"
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build_hdk_to_cl_dram_hbm_dma_readme: str = f"./{build_cl_examples}/{cl_dram_readme}"
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build_hdk_to_cl_sde_readme: str = f"./{build_cl_examples}/cl_sde/README.html"
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build_docs_to_repo_root: str = f"../{build_hdk_to_repo_root}"
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build_hdk_docs_to_images: str = "../../../build/html/_images"
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build_vitis_to_repo_root = "../../../.."
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extlinks = {
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"build-hdk-to-cl-example": (f"{build_hdk_to_cl_examples_root}/%s", "%s"),
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"build-hdk-to-repo-root": (f"{build_hdk_to_repo_root}/%s", "%s"),
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"build-hdk-to-cl-root": (f"{build_hdk_to_repo_root}/hdk/cl/examples/%s", "%s"),
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"supported-ddr-modes": (f"./{build_docs}/%s.html", "%s"),
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"cl-template-build-scripts": (f"{build_hdk_to_cl_template_build_scripts}/%s", "%s"),
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"cl-template-build-constraints": (f"{build_hdk_to_cl_template_build_constraints}/%s", "%s"),
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"common-shell-stable-build-scripts": (f"{build_hdk_to_hdk_common_shell_stable_build_scripts}/%s", "%s"),
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"build-hdk-to-cl-readme": (f"{build_cl_examples}/%s/README.html", "%s"),
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"run-rtl-sims": (f"{build_docs}/%s.html", "%s"),
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"shell-interface-spec": (f"{build_docs}/%s.html", "%s"),
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"pcie-memory-map": (f"{build_docs}/%s.html", "%s"),
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"build-hdk-docs-to-repo-root": (f"{build_docs_to_repo_root}/%s", "%s"),
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"docs-to-cl-mem-perf": (f"../{build_cl_examples}/%s", "%s"),
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"build-vitis-to-repo-root": (f"{build_vitis_to_repo_root}/%s", "%s"),
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}
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# -- Options for HTML output ---------------------------------------------------
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# The theme to use for HTML and HTML Help pages. See the documentation for
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# a list of builtin themes.
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html_theme = 'default'
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html_theme = 'sphinx_book_theme'
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# Theme options are theme-specific and customize the look and feel of a theme
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# further. For a list of options available for each theme, see the
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# documentation.
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#html_theme_options = {}
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html_context = {
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# ...
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"default_mode": "light"
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}
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html_theme_options = {
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"repository_url": "https://github.com/aws/aws-fpga" ,
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"use_issues_button": True,
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"use_repository_button": True,
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"use_download_button" : True,
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"use_fullscreen_button" : True,
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"use_edit_page_button": True,
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"repository_branch" : "f2",
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#"navbar_persistent": [],
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}
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#html_theme_path = []
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‎docs-rtd/source/developer_resources/DCV.rst

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DCV for their remote visualization requirements. Please refer to the
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`Official DCV
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documentation <https://docs.aws.amazon.com/dcv/latest/adminguide/what-is-dcv.html>`__
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`Back to Home <../index.html>`__

‎docs-rtd/source/hdk/README.rst

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<./docs/AWS_Shell_Interface_Specification.html>`__ and `PCIe Memory Map
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- Create your own CL designs or port F1 designs over to F2 systems
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Additional HDK Documentation
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----------------------------
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.. toctree::
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:maxdepth: 1
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docs/AWS_CLK_GEN_spec
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docs/Clock_Recipes_User_Guide
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docs/AWS_Shell_ERRATA
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docs/AWS_Shell_Interface_Specification
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docs/shell_floorplan
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docs/AWS_Fpga_Pcie_Memory_Map
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docs/RTL_Simulation_Guide_for_HDK_Design_Flow
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docs/on_premise_licensing_help
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docs/Supported_DDR_Modes
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docs/Virtual_JTAG_XVC
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`Back to Home <../index.html>`__

‎docs-rtd/source/hdk/cl/CHECKLIST_BEFORE_BUILDING_CL.rst

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`Back to HDK README <../index.html>`__

‎docs-rtd/source/hdk/cl/examples/CL_TEMPLATE/README.rst

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All examples use the same SystemVerilog `test
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`AWS_FPGA_REPO_DIR/hdk/common/verif <https://github.com/aws/aws-fpga/tree/f2/hdk/common/verif>`__.
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`AWS_FPGA_REPO_DIR/hdk/common/verif <https://github.com/aws/aws-fpga/tree/f2/hdk/common/verif>`__.
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This includes a `common Makefile flow <https://github.com/aws/aws-fpga/tree/f2/hdk/common/verif/tb/scripts>`__ that expects a
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`Makefile.tests <https://github.com/aws/aws-fpga/tree/f2/hdk/cl/examples/cl_sde/verif/scripts/Makefile.tests>`__ file that exposes Makefile targets for
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`Back to HDK README <../../../README.html>`__

‎docs-rtd/source/hdk/cl/examples/cl_dram_hbm_dma/README.rst

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CL_DRAM_HBM_DMA CustomLogic Example
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===================================
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CL_DRAM_HBM_DMA Custom Logic Example
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====================================
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3. `Software <#software>`__
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Overview
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|cl_dram_hbm_dma|
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Functional Description
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Simulations
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-----------
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Please see more details on running simulations in this
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`README <./verif/README.html>`__
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`Back to HDK README <../../../README.html>`__

‎docs-rtd/source/hdk/cl/examples/cl_dram_hbm_dma/verif/README.rst

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guide <../../../../docs/RTL_Simulation_Guide_for_HDK_Design_Flow.html>`__.
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`Back to HDK README <../../../../README.html>`__

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