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flatten designs for integration/verification
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@asinghani
asinghani committed May 16, 2023
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90 changes: 90 additions & 0 deletions designs/d01_example_adder/flattened.v
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/* Generated by Yosys 0.25+83 (git sha1 755b753e1, aarch64-apple-darwin20.2-clang 10.0.0-4ubuntu1 -fPIC -Os) */

/* top = 1 */
/* src = "d01_example_adder/src/toplevel_chip.v:4.1-18.10" */
module d01_example_adder(io_in, io_out);
wire _00_;
wire _01_;
wire _02_;
wire _03_;
wire _04_;
wire _05_;
wire _06_;
wire _07_;
wire _08_;
wire _09_;
wire _10_;
wire _11_;
wire _12_;
wire _13_;
wire _14_;
wire _15_;
wire _16_;
wire _17_;
wire _18_;
wire _19_;
wire _20_;
wire _21_;
wire _22_;
wire _23_;
wire _24_;
wire _25_;
/* src = "d01_example_adder/src/toplevel_chip.v:5.18-5.23" */
input [13:0] io_in;
wire [13:0] io_in;
/* src = "d01_example_adder/src/toplevel_chip.v:6.19-6.25" */
output [13:0] io_out;
wire [13:0] io_out;
/* hdlname = "mchip clock" */
/* src = "d01_example_adder/src/toplevel_chip.v:9.13-14.6|d01_example_adder/src/chip.sv:5.17-5.22" */
/* unused_bits = "0" */
wire \mchip.clock ;
/* hdlname = "mchip io_in" */
/* src = "d01_example_adder/src/toplevel_chip.v:9.13-14.6|d01_example_adder/src/chip.sv:4.24-4.29" */
wire [11:0] \mchip.io_in ;
/* hdlname = "mchip io_out" */
/* src = "d01_example_adder/src/toplevel_chip.v:9.13-14.6|d01_example_adder/src/chip.sv:6.25-6.31" */
wire [11:0] \mchip.io_out ;
/* hdlname = "mchip reset" */
/* src = "d01_example_adder/src/toplevel_chip.v:9.13-14.6|d01_example_adder/src/chip.sv:5.24-5.29" */
/* unused_bits = "0" */
wire \mchip.reset ;
assign _00_ = io_in[11] ^ io_in[5];
assign _01_ = ~(io_in[10] ^ io_in[4]);
assign _02_ = _00_ & ~(_01_);
assign _03_ = ~(io_in[9] & io_in[3]);
assign _04_ = io_in[9] ^ io_in[3];
assign _05_ = ~(io_in[8] & io_in[2]);
assign _06_ = _04_ & ~(_05_);
assign _07_ = _03_ & ~(_06_);
assign _08_ = ~(io_in[8] ^ io_in[2]);
assign _09_ = _04_ & ~(_08_);
assign _10_ = ~(io_in[7] & io_in[1]);
assign _11_ = io_in[7] ^ io_in[1];
assign _12_ = ~(io_in[6] & io_in[0]);
assign _13_ = _11_ & ~(_12_);
assign _14_ = _10_ & ~(_13_);
assign _15_ = _09_ & ~(_14_);
assign _16_ = _07_ & ~(_15_);
assign _17_ = _02_ & ~(_16_);
assign _18_ = ~(io_in[10] & io_in[4]);
assign _19_ = _00_ & ~(_18_);
assign _20_ = io_in[11] & io_in[5];
assign _21_ = _20_ | _19_;
assign io_out[6] = _21_ | _17_;
assign io_out[1] = ~(_12_ ^ _11_);
assign io_out[2] = _14_ ^ _08_;
assign _22_ = ~(_14_ | _08_);
assign _23_ = _22_ | ~(_05_);
assign io_out[3] = _23_ ^ _04_;
assign io_out[4] = _16_ ^ _01_;
assign _24_ = ~(_16_ | _01_);
assign _25_ = _24_ | ~(_18_);
assign io_out[5] = _25_ ^ _00_;
assign io_out[0] = io_in[6] ^ io_in[0];
assign io_out[13:7] = 7'h00;
assign \mchip.clock = io_in[12];
assign \mchip.io_in = io_in[11:0];
assign \mchip.io_out = { 5'h00, io_out[6:0] };
assign \mchip.reset = io_in[13];
endmodule
18 changes: 18 additions & 0 deletions designs/d01_example_adder/flattened_stats.txt
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=== d01_example_adder ===

Number of wires: 32
Number of wire bits: 80
Number of public wires: 6
Number of public wire bits: 54
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 33
$_ANDNOT_ 10
$_AND_ 1
$_NAND_ 5
$_NOR_ 2
$_ORNOT_ 2
$_OR_ 2
$_XNOR_ 3
$_XOR_ 8
230 changes: 230 additions & 0 deletions designs/d02_example_counter/flattened.v
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/* Generated by Yosys 0.25+83 (git sha1 755b753e1, aarch64-apple-darwin20.2-clang 10.0.0-4ubuntu1 -fPIC -Os) */

/* top = 1 */
/* src = "d02_example_counter/src/toplevel_chip.v:4.1-18.10" */
module d02_example_counter(io_in, io_out);
wire _000_;
wire _001_;
wire _002_;
wire _003_;
wire _004_;
wire _005_;
wire _006_;
wire _007_;
wire _008_;
wire _009_;
wire _010_;
wire _011_;
wire _012_;
wire _013_;
wire _014_;
wire _015_;
wire _016_;
wire _017_;
wire _018_;
wire _019_;
wire _020_;
wire _021_;
wire _022_;
wire _023_;
wire _024_;
wire _025_;
wire _026_;
wire _027_;
wire _028_;
wire _029_;
wire _030_;
wire _031_;
wire _032_;
wire _033_;
wire _034_;
wire _035_;
wire _036_;
wire _037_;
wire _038_;
wire _039_;
wire _040_;
wire _041_;
wire _042_;
wire _043_;
wire _044_;
wire _045_;
wire _046_;
wire _047_;
wire _048_;
wire _049_;
wire _050_;
wire _051_;
wire _052_;
wire _053_;
wire _054_;
wire _055_;
wire _056_;
wire _057_;
wire _058_;
/* force_downto = 32'd1 */
/* src = "d02_example_counter/src/toplevel_chip.v:9.13-14.6|d02_example_counter/src/chip.sv:18.23-18.33|/Users/anish/workspace/oss-cad-suite/libexec/../share/yosys/techmap.v:270.26-270.27" */
wire [11:0] _059_;
/* src = "d02_example_counter/src/toplevel_chip.v:5.18-5.23" */
input [13:0] io_in;
wire [13:0] io_in;
/* src = "d02_example_counter/src/toplevel_chip.v:6.19-6.25" */
output [13:0] io_out;
wire [13:0] io_out;
/* hdlname = "mchip clock" */
/* src = "d02_example_counter/src/toplevel_chip.v:9.13-14.6|d02_example_counter/src/chip.sv:5.17-5.22" */
wire \mchip.clock ;
/* hdlname = "mchip enable" */
/* src = "d02_example_counter/src/toplevel_chip.v:9.13-14.6|d02_example_counter/src/chip.sv:9.11-9.17" */
wire \mchip.enable ;
/* hdlname = "mchip io_in" */
/* src = "d02_example_counter/src/toplevel_chip.v:9.13-14.6|d02_example_counter/src/chip.sv:4.24-4.29" */
/* unused_bits = "2 3 4 5 6 7 8 9 10 11" */
wire [11:0] \mchip.io_in ;
/* hdlname = "mchip io_out" */
/* src = "d02_example_counter/src/toplevel_chip.v:9.13-14.6|d02_example_counter/src/chip.sv:6.25-6.31" */
reg [11:0] \mchip.io_out ;
/* hdlname = "mchip reset" */
/* src = "d02_example_counter/src/toplevel_chip.v:9.13-14.6|d02_example_counter/src/chip.sv:5.24-5.29" */
wire \mchip.reset ;
/* hdlname = "mchip updown" */
/* src = "d02_example_counter/src/toplevel_chip.v:9.13-14.6|d02_example_counter/src/chip.sv:9.19-9.25" */
wire \mchip.updown ;
assign _059_[0] = ~\mchip.io_out [0];
assign _001_ = ~(io_in[1] & io_in[0]);
assign _002_ = io_in[1] | ~(io_in[0]);
assign _000_ = ~(_002_ & _001_);
assign _003_ = _001_ ^ \mchip.io_out [1];
assign _059_[1] = _003_ ^ _059_[0];
assign _004_ = \mchip.io_out [1] & ~(_001_);
assign _005_ = \mchip.io_out [0] & ~(_003_);
assign _006_ = _005_ | _004_;
assign _007_ = _001_ ^ \mchip.io_out [2];
assign _059_[2] = ~(_007_ ^ _006_);
assign _008_ = \mchip.io_out [2] & ~(_001_);
assign _009_ = _006_ & ~(_007_);
assign _010_ = ~(_009_ | _008_);
assign _011_ = _001_ ^ \mchip.io_out [3];
assign _059_[3] = _011_ ^ _010_;
assign _012_ = _011_ | _007_;
assign _013_ = _006_ & ~(_012_);
assign _014_ = \mchip.io_out [3] & ~(_001_);
assign _015_ = _008_ & ~(_011_);
assign _016_ = _015_ | _014_;
assign _017_ = _016_ | _013_;
assign _018_ = _001_ ^ \mchip.io_out [4];
assign _059_[4] = ~(_018_ ^ _017_);
assign _019_ = \mchip.io_out [4] & ~(_001_);
assign _020_ = _017_ & ~(_018_);
assign _021_ = ~(_020_ | _019_);
assign _022_ = _001_ ^ \mchip.io_out [5];
assign _059_[5] = _022_ ^ _021_;
assign _023_ = _022_ | _018_;
assign _024_ = _017_ & ~(_023_);
assign _025_ = \mchip.io_out [5] & ~(_001_);
assign _026_ = _019_ & ~(_022_);
assign _027_ = _026_ | _025_;
assign _028_ = _027_ | _024_;
assign _029_ = _001_ ^ \mchip.io_out [6];
assign _059_[6] = ~(_029_ ^ _028_);
assign _030_ = \mchip.io_out [6] & ~(_001_);
assign _031_ = _028_ & ~(_029_);
assign _032_ = ~(_031_ | _030_);
assign _033_ = _001_ ^ \mchip.io_out [7];
assign _059_[7] = _033_ ^ _032_;
assign _034_ = \mchip.io_out [7] & ~(_001_);
assign _035_ = _030_ & ~(_033_);
assign _036_ = _035_ | _034_;
assign _037_ = _033_ | _029_;
assign _038_ = _027_ & ~(_037_);
assign _039_ = _038_ | _036_;
assign _040_ = _037_ | _023_;
assign _041_ = _017_ & ~(_040_);
assign _042_ = _041_ | _039_;
assign _043_ = ~(_001_ ^ \mchip.io_out [8]);
assign _059_[8] = _043_ ^ _042_;
assign _044_ = \mchip.io_out [8] & ~(_001_);
assign _045_ = _043_ & _042_;
assign _046_ = _045_ | _044_;
assign _047_ = ~(_001_ ^ \mchip.io_out [9]);
assign _059_[9] = _047_ ^ _046_;
assign _048_ = \mchip.io_out [9] & ~(_001_);
assign _049_ = _047_ & _044_;
assign _050_ = _049_ | _048_;
assign _051_ = ~(_047_ & _043_);
assign _052_ = _042_ & ~(_051_);
assign _053_ = _052_ | _050_;
assign _054_ = ~(_001_ ^ \mchip.io_out [10]);
assign _059_[10] = _054_ ^ _053_;
assign _055_ = \mchip.io_out [10] & ~(_001_);
assign _056_ = _054_ & _053_;
assign _057_ = _056_ | _055_;
assign _058_ = ~(_001_ ^ \mchip.io_out [11]);
assign _059_[11] = _058_ ^ _057_;
/* \always_ff = 32'd1 */
/* src = "d02_example_counter/src/toplevel_chip.v:9.13-14.6|d02_example_counter/src/chip.sv:13.5-23.8" */
always @(posedge io_in[12])
if (io_in[13]) \mchip.io_out [0] <= 1'h0;
else if (_000_) \mchip.io_out [0] <= _059_[0];
/* \always_ff = 32'd1 */
/* src = "d02_example_counter/src/toplevel_chip.v:9.13-14.6|d02_example_counter/src/chip.sv:13.5-23.8" */
always @(posedge io_in[12])
if (io_in[13]) \mchip.io_out [1] <= 1'h0;
else if (_000_) \mchip.io_out [1] <= _059_[1];
/* \always_ff = 32'd1 */
/* src = "d02_example_counter/src/toplevel_chip.v:9.13-14.6|d02_example_counter/src/chip.sv:13.5-23.8" */
always @(posedge io_in[12])
if (io_in[13]) \mchip.io_out [2] <= 1'h0;
else if (_000_) \mchip.io_out [2] <= _059_[2];
/* \always_ff = 32'd1 */
/* src = "d02_example_counter/src/toplevel_chip.v:9.13-14.6|d02_example_counter/src/chip.sv:13.5-23.8" */
always @(posedge io_in[12])
if (io_in[13]) \mchip.io_out [3] <= 1'h0;
else if (_000_) \mchip.io_out [3] <= _059_[3];
/* \always_ff = 32'd1 */
/* src = "d02_example_counter/src/toplevel_chip.v:9.13-14.6|d02_example_counter/src/chip.sv:13.5-23.8" */
always @(posedge io_in[12])
if (io_in[13]) \mchip.io_out [4] <= 1'h0;
else if (_000_) \mchip.io_out [4] <= _059_[4];
/* \always_ff = 32'd1 */
/* src = "d02_example_counter/src/toplevel_chip.v:9.13-14.6|d02_example_counter/src/chip.sv:13.5-23.8" */
always @(posedge io_in[12])
if (io_in[13]) \mchip.io_out [5] <= 1'h0;
else if (_000_) \mchip.io_out [5] <= _059_[5];
/* \always_ff = 32'd1 */
/* src = "d02_example_counter/src/toplevel_chip.v:9.13-14.6|d02_example_counter/src/chip.sv:13.5-23.8" */
always @(posedge io_in[12])
if (io_in[13]) \mchip.io_out [6] <= 1'h0;
else if (_000_) \mchip.io_out [6] <= _059_[6];
/* \always_ff = 32'd1 */
/* src = "d02_example_counter/src/toplevel_chip.v:9.13-14.6|d02_example_counter/src/chip.sv:13.5-23.8" */
always @(posedge io_in[12])
if (io_in[13]) \mchip.io_out [7] <= 1'h0;
else if (_000_) \mchip.io_out [7] <= _059_[7];
/* \always_ff = 32'd1 */
/* src = "d02_example_counter/src/toplevel_chip.v:9.13-14.6|d02_example_counter/src/chip.sv:13.5-23.8" */
always @(posedge io_in[12])
if (io_in[13]) \mchip.io_out [8] <= 1'h0;
else if (_000_) \mchip.io_out [8] <= _059_[8];
/* \always_ff = 32'd1 */
/* src = "d02_example_counter/src/toplevel_chip.v:9.13-14.6|d02_example_counter/src/chip.sv:13.5-23.8" */
always @(posedge io_in[12])
if (io_in[13]) \mchip.io_out [9] <= 1'h0;
else if (_000_) \mchip.io_out [9] <= _059_[9];
/* \always_ff = 32'd1 */
/* src = "d02_example_counter/src/toplevel_chip.v:9.13-14.6|d02_example_counter/src/chip.sv:13.5-23.8" */
always @(posedge io_in[12])
if (io_in[13]) \mchip.io_out [10] <= 1'h0;
else if (_000_) \mchip.io_out [10] <= _059_[10];
/* \always_ff = 32'd1 */
/* src = "d02_example_counter/src/toplevel_chip.v:9.13-14.6|d02_example_counter/src/chip.sv:13.5-23.8" */
always @(posedge io_in[12])
if (io_in[13]) \mchip.io_out [11] <= 1'h0;
else if (_000_) \mchip.io_out [11] <= _059_[11];
assign io_out = { 2'h0, \mchip.io_out };
assign \mchip.clock = io_in[12];
assign \mchip.enable = io_in[0];
assign \mchip.io_in = io_in[11:0];
assign \mchip.reset = io_in[13];
assign \mchip.updown = io_in[1];
endmodule
20 changes: 20 additions & 0 deletions designs/d02_example_counter/flattened_stats.txt
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=== d02_example_counter ===

Number of wires: 68
Number of wire bits: 127
Number of public wires: 8
Number of public wire bits: 56
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 83
$_ANDNOT_ 22
$_AND_ 3
$_NAND_ 3
$_NOR_ 3
$_NOT_ 1
$_ORNOT_ 1
$_OR_ 16
$_SDFFE_PP0P_ 12
$_XNOR_ 7
$_XOR_ 15
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