theoretically remove async resets

asinghani · May 16, 2023 · 5981739 · 5981739
1 parent f86296f
commit 5981739
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Showing 19 changed files with 34 additions and 34 deletions.
diff --git a/designs/d15_jerryfen_prng/src/chip.sv b/designs/d15_jerryfen_prng/src/chip.sv
@@ -133,7 +133,7 @@ module control_path
         endcase
     end
 
-    always_ff @(posedge clock, posedge reset) begin
+    always_ff @(posedge clock) begin
 
         if (reset) begin
             curr_state <= reset_state;
@@ -175,7 +175,7 @@ module fibo_lsfr
 
     logic feedback;
 
-    always_ff @(posedge clk, posedge reset) begin
+    always_ff @(posedge clk) begin
 
         if(reset)
             state_out <= 8'b0;
@@ -222,7 +222,7 @@ module galo_lsfr
     // xor G2(state_out[5], state_out[4], nextbit);
     // xor G3(state_out[4], state_out[3], nextbit);
 
-    always_ff @(posedge clk, posedge reset) begin
+    always_ff @(posedge clk) begin
 
         if(reset)
             state_out <= 8'b0000_0000;

diff --git a/designs/d15_jerryfen_prng/src/library.sv b/designs/d15_jerryfen_prng/src/library.sv
@@ -122,7 +122,7 @@ module DFlipFlop
   (input logic D, preset_L, reset_L, clock,
    output logic Q);
 
-   always_ff @(posedge clock, negedge reset_L) begin
+   always_ff @(posedge clock) begin
 
      if(~preset_L)
        Q <= 1;
@@ -165,7 +165,7 @@ module width_FlipFlop
    input logic [WIDTH-1:0] D,
    output logic [WIDTH-1:0] Q);
 
-   always_ff @(posedge clock, negedge reset_L) begin
+   always_ff @(posedge clock) begin
 
      if(~preset_L)
        Q <= 8'b1;

diff --git a/designs/d18_nikhildj_mac/src/DFF.sv b/designs/d18_nikhildj_mac/src/DFF.sv
@@ -4,7 +4,7 @@ module DFF (
     input logic D,
     output logic Q
 );
-    always_ff @(posedge clk, negedge reset) begin
+    always_ff @(posedge clk) begin
         if (!reset) begin
             Q <= 0;     // Clear the register
         end else begin

diff --git a/designs/d18_nikhildj_mac/src/mac_controller.sv b/designs/d18_nikhildj_mac/src/mac_controller.sv
@@ -13,7 +13,7 @@ module CONTROLLER_MAC (
     logic [3:0] temp_count;
     enum logic [2:0] {IDLE, INIT, LOAD, RUN, TEST, ADD} state;
 
-    always_ff @(posedge clk or negedge reset) begin
+    always_ff @(posedge clk) begin
         if (!reset) begin
             state      <= IDLE;
             temp_count <= 4'b1001;

diff --git a/designs/d18_nikhildj_mac/src/multiplier.sv b/designs/d18_nikhildj_mac/src/multiplier.sv
@@ -15,7 +15,7 @@ module MULTIPLIER_RESULT (
     logic [16:0] temp_register;
     logic temp_Add;
 
-    always_ff @(posedge clk or negedge reset) begin
+    always_ff @(posedge clk) begin
         if (!reset) begin
             temp_register <= '0;
             temp_Add     <= 1'b0;

diff --git a/designs/d18_nikhildj_mac/src/multiplier_controller.sv b/designs/d18_nikhildj_mac/src/multiplier_controller.sv
@@ -12,7 +12,7 @@ module CONTROLLER (
     logic [2:0] temp_count;
     enum logic [3:0] {IDLE, INIT, TEST, ADD, SHIFT} state;
 
-    always_ff @(posedge clk or negedge reset) begin
+    always_ff @(posedge clk) begin
         if (!reset) begin
             state      <= IDLE;
             temp_count <= 3'b000;

diff --git a/designs/d22_yushuanl_convolution/src/chip.sv b/designs/d22_yushuanl_convolution/src/chip.sv
@@ -152,9 +152,9 @@ module my_chip
       default: nextState = Start;
     endcase
   end
-  always_ff @(posedge clock, posedge reset)
+  always_ff @(posedge clock)
     if (reset)
       curState <= Start;
     else
       curState <= nextState;
-endmodule
+endmodule
diff --git a/designs/d23_zhiyingm_turing/TuringMachine/TuringMachine.sv b/designs/d23_zhiyingm_turing/TuringMachine/TuringMachine.sv
@@ -221,10 +221,10 @@ module FSM (
   end
 
   // Asynchronous state reset
-  always_ff @(posedge clock, posedge reset)
+  always_ff @(posedge clock)
     if (reset)
       currState <= START;
     else
       currState <= nextState;
 
-endmodule: FSM
+endmodule: FSM
diff --git a/designs/d23_zhiyingm_turing/TuringMachine/library.sv b/designs/d23_zhiyingm_turing/TuringMachine/library.sv
@@ -49,7 +49,7 @@ module DFlipFlop // stores 1 bit value
    input  logic clock, reset_L, preset_L,
    output logic Q);
 
-  always_ff @(posedge clock, negedge reset_L, negedge preset_L) begin
+  always_ff @(posedge clock) begin
     // asynchronous reset and preset, active low
     if (~reset_L)
       Q <= 1'b0;
@@ -152,4 +152,4 @@ module Memory_synth // stores a number of words, conbinational read, sequential
       M[addr] <= data_in; // synchronized write
   end
 
-endmodule: Memory_synth
+endmodule: Memory_synth
diff --git a/designs/d23_zhiyingm_turing/src/TuringMachine.sv b/designs/d23_zhiyingm_turing/src/TuringMachine.sv
@@ -211,10 +211,10 @@ module FSM (
   end
 
   // Asynchronous state reset
-  always_ff @(posedge clock, posedge reset)
+  always_ff @(posedge clock)
     if (reset)
       currState <= START;
     else
       currState <= nextState;
 
-endmodule: FSM
+endmodule: FSM
diff --git a/designs/d23_zhiyingm_turing/src/library.sv b/designs/d23_zhiyingm_turing/src/library.sv
@@ -49,7 +49,7 @@ module DFlipFlop // stores 1 bit value
    input  logic clock, reset_L, preset_L,
    output logic Q);
 
-  always_ff @(posedge clock, negedge reset_L, negedge preset_L) begin
+  always_ff @(posedge clock) begin
     // asynchronous reset and preset, active low
     if (~reset_L)
       Q <= 1'b0;
@@ -152,4 +152,4 @@ module Memory_synth // stores a number of words, conbinational read, sequential
       M[addr] <= data_in; // synchronized write
   end
 
-endmodule: Memory_synth
+endmodule: Memory_synth
diff --git a/designs/d26_cjstange_perceptron/src/lib.sv b/designs/d26_cjstange_perceptron/src/lib.sv
@@ -4,7 +4,7 @@ module counter
     (input  logic             clk, reset_l, en, clr,
      output logic [WIDTH-1:0] count);
 
-    always_ff @(posedge clk, negedge reset_l) begin
+    always_ff @(posedge clk) begin
         if (!reset_l)
             count <= 'b0;
         else if (clr)
@@ -22,7 +22,7 @@ module register
      input  logic [WIDTH-1:0]   D,
      output logic [WIDTH-1:0]   Q);
 
-    always_ff @(posedge clk, negedge reset_l) begin
+    always_ff @(posedge clk) begin
         if (!reset_l)
             Q <= 'b0;
         else if (en)
@@ -63,4 +63,4 @@ module adder
      output logic [WIDTH-1:0]   sum);
 
     assign {cout, sum} = A + B + cin;
-endmodule: adder
+endmodule: adder
diff --git a/designs/d26_cjstange_perceptron/src/lib.v b/designs/d26_cjstange_perceptron/src/lib.v
@@ -10,7 +10,7 @@ module counter (clk,
 	input wire clr;
 	output reg [WIDTH - 1:0] count;
 
-	always @(posedge clk or negedge reset_l)
+	always @(posedge clk)
 		if (!reset_l)
 			count <= 'b0;
 		else if (clr)
@@ -31,7 +31,7 @@ module register (clk,
 	input wire [WIDTH - 1:0] D;
 	output reg [WIDTH - 1:0] Q;
 
-	always @(posedge clk or negedge reset_l)
+	always @(posedge clk)
 		if (!reset_l)
 			Q <= 'b0;
 		else if (en)
@@ -75,4 +75,4 @@ module adder (cin,
 	output wire [WIDTH - 1:0] sum;
 
 	assign {cout, sum} = (A + B) + cin;
-endmodule
+endmodule
diff --git a/designs/d26_cjstange_perceptron/src/perceptron.sv b/designs/d26_cjstange_perceptron/src/perceptron.sv
@@ -372,10 +372,10 @@ module fsm
         endcase
     end
 
-    always_ff @(posedge clk, negedge reset_l) begin
+    always_ff @(posedge clk) begin
         if (!reset_l)
             state <= INIT;
         else
             state <= nextState;
     end
-endmodule
+endmodule
diff --git a/designs/d30_yuchingw_fpga/src/chip.sv b/designs/d30_yuchingw_fpga/src/chip.sv
@@ -6,7 +6,7 @@ module Register
     input logic [W-1:0] D,
     output logic [W-1:0] Q
 );
-    always_ff @(posedge clock, posedge reset) begin
+    always_ff @(posedge clock) begin
         if (reset) begin
             Q <= 'd0;
         end else if (en) begin
@@ -25,7 +25,7 @@ module Counter
     input logic reset, clock, en,
     output logic [W-1:0] Q
 );
-    always_ff @(posedge clock, posedge reset) begin
+    always_ff @(posedge clock) begin
         if (reset) begin
             Q <= 'd0;
         end else if (en) begin

diff --git a/designs/d37_sophiali_calculator/src/math.sv b/designs/d37_sophiali_calculator/src/math.sv
@@ -31,7 +31,7 @@ module sophialiCMU_math (
   enum logic {IDLE, GO} state, nextState;
 
   // ALU
-  always_ff @(posedge clock, posedge reset) begin
+  always_ff @(posedge clock) begin
     if (reset)
       io_out <= 0;
     else begin
@@ -46,7 +46,7 @@ module sophialiCMU_math (
   end
 
   // FF to ensure button for enable isn't continuously set
-  always_ff @(posedge clock, posedge reset) begin
+  always_ff @(posedge clock) begin
     if (reset)
       state <= IDLE;
     else begin

diff --git a/designs/d40_jrecta_asyncfifo/src/async-fifo.sv b/designs/d40_jrecta_asyncfifo/src/async-fifo.sv
@@ -101,7 +101,7 @@ module reg_ar
   (input logic clk, rst, en,
    input logic[WIDTH-1:0] d,
    output logic[WIDTH-1:0] q);
-  always_ff @(posedge clk, posedge rst)
+  always_ff @(posedge clk)
     if(rst)
       q <= '0;
     else if(en)

diff --git a/designs/d41_stroucki_corralgame/src/game.sv b/designs/d41_stroucki_corralgame/src/game.sv
@@ -190,7 +190,7 @@ module game
     end
 
   // state transition  
-  always @(posedge clock, negedge reset_n) begin
+  always @(posedge clock) begin
     if (~reset_n) begin
       lostwon <= 1;
       state <= SETUP;

diff --git a/designs/d41_stroucki_corralgame/src/stroucki_top.sv b/designs/d41_stroucki_corralgame/src/stroucki_top.sv
@@ -62,7 +62,7 @@ module stroucki_top
     endcase
   end
 
-  always @(posedge clock, negedge reset_n) begin
+  always @(posedge clock) begin
     if (~reset_n) begin
       state <= IDLE;
       data <= 4'b0;