updates to MUX architecture

designs/d02_example_counter/standard_tb.sv

@@ -0,0 +1,34 @@
+`default_nettype none
+
+`define ASSERT(x) if (!(x)) begin \
+    $display("Assert failed at line %d", `__LINE__); \
+    $finish(1); \
+end
+
+module standard_tb (
+    output logic [11:0] io_in,
+    input logic [11:0] io_out,
+    input logic ready,
+    input logic clock, reset
+);
+
+    initial begin
+        io_in = 0;
+
+        #100;
+        while (!ready) @(negedge clock);
+
+        $monitor("[%d] out=%d, en=%d, ud=%d", $time, io_out, io_in[0], io_in[1]);
+
+        io_in[0] = 1;
+        repeat(100) @(negedge clock);
+        io_in[0] = 0;
+        repeat(100) @(negedge clock);
+        io_in[0] = 1;
+        io_in[1] = 1;
+        repeat(100) @(negedge clock);
+
+        $finish(0); // pass
+    end
+
+endmodule

designs/d05_meta_info/tb.v

@@ -5,8 +5,9 @@ module tb;
 
     wire [7:0] chr;
 
-    d05_meta_info chip (
-        .io_in({reset, clock, proj_idx, chr_idx}),
+    my_chip chip (
+        .reset, .clock,
+        .io_in({proj_idx, chr_idx}),
         .io_out(chr)
     );
 

designs/d14_jessief_trafficlight/test_wrapped.sv

@@ -0,0 +1,106 @@
+`default_nettype none
+
+module clock_maker
+  (output logic clock);
+
+  initial begin
+    clock = 1'b1;
+    forever #1 clock = ~clock;
+  end
+
+endmodule: clock_maker
+
+module test ();
+  logic clock, reset, car1, car2, car3, car4, ped, 
+                stop_yellow, stop_ped, stop_five,
+                red1, yellow1, green1, 
+                red2, yellow2, green2,
+                red3, yellow3, green3,
+                turn, orange, white, 
+                yellow_en, 
+                yellow_clr, 
+                stop_en,
+                stop_clr, 
+                five_en,
+                five_clr, 
+                ped_clr,
+                button;
+
+    clock_maker clocky(.*);
+
+    my_chip mchip (
+        .clock, .reset,
+        .io_in({7'b0, car1, car2, car3, car4, button}),
+        .io_out({red1, yellow1, green1, 
+                red2, yellow2, green2,
+                red3, yellow3, green3,
+                turn, orange, white})
+    );
+
+  initial begin
+      $monitor($time,,  "\n",
+      "_________________________________________________________________________\n",
+      "                                             |_|  red    %b              \n", red3,
+      "                                             |_|  yellow %b  <-- car %b  \n", yellow3, car3,
+      "                                             |_|  green  %b              \n", green3,
+      "- - - - - - - - - - -                        |_|  turn   %b      car %b  \n", turn, car4,
+      "           red    %b                          |_|  - - - - - - - - - - - -\n", red1,
+      "car %b -->  yellow %b                          |_|                         \n", car1, yellow1,
+      "           green  %b                          |_|                         \n", green1,
+      "______________________                       ____________________________\n",
+      "                      |         | red    %b  | cross %b                   \n", red2, white,
+      "                      |           yellow %b  | stop  %b                   \n", yellow2, orange,
+      "                      |         | green  %b  |    ^                      \n", green2,
+      "                      |              ^      |    |                       \n",
+      "                      |         |    |      |   ped %b                       \n", ped,
+      "                      |            car %b    |                            \n", car2);
+
+    //initialize
+    button <= 1'b0;
+    car1 <= 1'b0;
+    car2 <= 1'b0;
+    car3 <= 1'b0;
+    car4 <= 1'b0;
+    reset <= 1'b0;
+    @(posedge clock);
+    reset <= 1'b1;
+    @(posedge clock);
+    reset <= 1'b0;
+    @(posedge clock);
+
+    //test each car/ped individually
+    button <= 1'b1;
+    @(posedge clock);
+    car1 <= 1'b1;
+    @(posedge clock);
+    @(posedge clock);
+    @(posedge clock);
+    @(posedge clock);
+    button <= 1'b0;
+    car1 <= 1'b0;
+    @(posedge clock);
+    @(posedge clock);
+    @(posedge clock);
+    @(posedge clock);
+    car2 <= 1'b1;
+    @(posedge clock);
+    @(posedge clock);
+    @(posedge clock);
+    car2 <= 1'b0;
+    @(posedge clock);
+    @(posedge clock);
+    @(posedge clock);
+    @(posedge clock);
+    car3 <= 1'b1;
+    car4 <= 1'b1;
+    @(posedge clock);
+    @(posedge clock);
+    @(posedge clock);
+    @(posedge clock);
+    @(posedge clock);
+    @(posedge clock);
+    @(posedge clock);
+    $finish;
+  end
+
+endmodule: test

top_level/design_tb_wrap.sv

@@ -0,0 +1,13 @@
+module my_chip (
+    input logic [11:0] io_in,
+    output logic [11:0] io_out,
+    input logic clock,
+    input logic reset
+);
+    design_instantiations dut (
+        .io_in, .io_out,
+        .clock, .reset,
+        .des_sel(6'd`DES_NUM), .hold_if_not_sel(1'b0)
+    );
+
+endmodule

top_level/gen-wrapped-tb.sh

@@ -0,0 +1,9 @@
+#!/bin/sh
+DES_NAME=$1
+DES_NUM=$(echo $DES_NAME | cut -d "_" -f 1 | tr -d "d")
+
+rm -r build || true
+mkdir -p build
+sv2v --define=DES_NUM=$DES_NUM design_tb_wrap.sv > build/mwrap.v
+cat build/mwrap.v design_instantiations_flattened.v > "build/des"$DES_NUM"_wrapped.v"
+echo "build/des"$DES_NUM"_wrapped.v"

top_level/multiplexer-ff.sv

@@ -0,0 +1,46 @@
+`default_nettype none
+
+module multiplexer (
+	input logic [11:0] io_in,
+	output logic [11:0] io_out,
+
+	input logic [5:0] des_sel,
+	input logic hold_if_not_sel,
+
+	output logic [11:0] des_io_in[0:63],
+	output logic des_reset[0:63],
+	input logic [11:0] des_io_out[0:63],
+
+	input logic clock, reset
+);
+
+    logic [63:0] des_sel_dec;
+    always_ff @(posedge clock) begin
+        des_sel_dec <= '0;
+        des_sel_dec[des_sel] <= 1;
+    end
+
+    integer i;
+    always_ff @(posedge clock) begin
+        io_out <= '0;
+
+        for (i = 0; i < 64; i++) begin
+            if (des_sel_dec[i]) begin
+                io_out <= des_io_out[i];
+            end
+
+            // hold_if_not_sel will hold all other designs
+            // in reset with all-zero inputs when set
+            if (hold_if_not_sel && (!des_sel_dec[i])) begin
+                des_io_in[i] <= '0;
+                des_reset[i] <= '1;
+            end
+
+            else begin
+                des_io_in[i] <= io_in;
+                des_reset[i] <= reset;
+            end
+        end
+    end
+
+endmodule

top_level/multiplexer.sv

@@ -29,7 +29,7 @@ module multiplexer (
                 io_out = des_io_out[i];
             end
 
-            // hold_if_not_sel will hold all other designs
+            // hold_if_not_sel will hold all others
             // in reset with all-zero inputs when set
             if (hold_if_not_sel && (!des_sel_dec[i])) begin
                 des_io_in[i] = '0;

top_level/verif/d05_meta_info.sh

@@ -0,0 +1,19 @@
+#!/bin/sh
+DES_NAME=d05_meta_info
+DES_NUM=$(echo $DES_NAME | cut -d "_" -f 1 | tr -d "d")
+TESTBENCH=tb.v
+
+cd $(dirname "$0")/..
+./gen-wrapped-tb.sh $DES_NAME
+
+rm build/tb.vvp || true
+rm build/tb_out.v || true
+
+sv2v ../designs/$DES_NAME/$TESTBENCH > build/tb_out.v
+iverilog -g2012 -o build/tb.vvp "build/des"$DES_NUM"_wrapped.v" build/tb_out.v
+
+echo ""
+echo ============ Starting TB for design $DES_NAME ============
+vvp build/tb.vvp
+echo $?
+echo ""

top_level/verif/d14_jessief_trafficlight.sh

@@ -0,0 +1,19 @@
+#!/bin/sh
+DES_NAME=d14_jessief_trafficlight
+DES_NUM=$(echo $DES_NAME | cut -d "_" -f 1 | tr -d "d")
+TESTBENCH=test_wrapped.sv
+
+cd $(dirname "$0")/..
+./gen-wrapped-tb.sh $DES_NAME
+
+rm build/tb.vvp || true
+rm build/tb_out.v || true
+
+sv2v ../designs/$DES_NAME/$TESTBENCH > build/tb_out.v
+iverilog -g2012 -o build/tb.vvp "build/des"$DES_NUM"_wrapped.v" build/tb_out.v
+
+echo ""
+echo ============ Starting TB for design $DES_NAME ============
+vvp build/tb.vvp
+echo $?
+echo ""