fix and add TB for d18

designs/d18_nikhildj_mac/flattened_stats.txt

@@ -1,28 +1,29 @@
 === d18_nikhildj_mac ===
 
-   Number of wires:                825
-   Number of wire bits:           1663
-   Number of public wires:         538
-   Number of public wire bits:    1376
+   Number of wires:                794
+   Number of wire bits:           1621
+   Number of public wires:         541
+   Number of public wire bits:    1368
    Number of memories:               0
    Number of memory bits:            0
    Number of processes:              0
-   Number of cells:                419
-     $_ANDNOT_                      98
-     $_AND_                         26
-     $_DFF_P_                       46
-     $_MUX_                         30
-     $_NAND_                        10
-     $_NOR_                         11
-     $_NOT_                         10
+   Number of cells:                410
+     $_ANDNOT_                      72
+     $_AND_                         25
+     $_DFFE_PP_                     35
+     $_DFF_P_                       15
+     $_MUX_                         49
+     $_NAND_                        12
+     $_NOR_                          8
+     $_NOT_                          8
      $_ORNOT_                       10
-     $_OR_                          65
+     $_OR_                          41
+     $_SDFFCE_PN0P_                  1
      $_SDFFE_NP0P_                   4
      $_SDFFE_PP0N_                   1
      $_SDFFE_PP0P_                  21
      $_SDFFE_PP1P_                   2
      $_SDFF_NP0_                    16
-     $_SDFF_PN0_                     1
-     $_SDFF_PP0_                    19
-     $_XNOR_                        14
-     $_XOR_                         35
+     $_SDFF_PP0_                    40
+     $_XNOR_                        16
+     $_XOR_                         34

designs/d18_nikhildj_mac/src/chip.sv

@@ -16,59 +16,38 @@ module my_chip (
      logic mac_carry_out;
      logic Finish;
     logic End_mul;
-    bit input_done = 1'b0;
-    bit output_done = 1'b0;
-
-assign reset_n = !reset;
-assign START = io_in[11];  
-assign  mac_carry_out =  io_out[11];
-assign Finish = io_out[10];
-    assign input_done = io_in[8];
-    assign output_done = io_out[8];
-    assign End_mul = io_out[7];
-
-    assign io_in[7:0] = 8'd0;
-    assign io_out[6:0] = 8'd0;
-
+    logic do_next;
+
+    assign reset_n = !reset;
+    assign START = io_in[11];  
+    assign do_next = io_in[7];
 
-integer i,j;
+    assign io_out[11] = mac_carry_out;
+    assign io_out[10] = Finish;
+    assign io_out[9] = shiftout[0];
+    assign io_out[8] = End_mul;
 
+    assign io_out[7:0] = 8'd0;
 
 
+    reg [19:0] shiftout;
+    reg shiftin;
+    reg _Finish;
+
     always@(posedge clock) begin
-
-        for (i=0;i<8;i = i+1) begin
-            op_a_in[i] <= io_in[10];
-            op_b_in[i] <= io_in[9];
-        end
-
-        if (i == 8) begin
-            input_done <= 1'b1;
-        end
-
-        else begin 
-            input_done <= 1'b0;
-        end
-
-        if (Finish) begin
-            for (j=0;j<20;j=j+1) begin
-                io_out[9] <=  mac_res[j];
-            end
-        end
-        else begin
-            io_out[9] <= 1'b0;
-        end
-
-
-        if (j == 20) begin
-            output_done <= 1'b1;
+        shiftin <= io_in[8];
+        _Finish <= Finish;
+
+        if (io_in[8] && !shiftin) begin
+            op_a_in <= {op_a_in, io_in[10]};
+            op_b_in <= {op_b_in, io_in[9]};
+            shiftout <= shiftout[19:1];
         end
-        
-        else begin 
-            output_done <= 1'b0;
+
+        if (Finish && ~_Finish) begin
+            shiftout <= mac_res;
         end
 
-
     end
 
 
@@ -100,7 +79,8 @@ CONTROLLER_MAC control (
     .RESET_cmd(control_reset),
     .Load_op(Load_op),
     .Begin_mul(Begin_mul),
-    .add(add)
+    .add(add),
+    .do_next(do_next)
 );
 
 register8 opa (

designs/d18_nikhildj_mac/src/mac_controller.sv

@@ -3,6 +3,7 @@ module CONTROLLER_MAC (
     input  logic clk,
     input  logic START,
     input  logic End_mul,
+    input  logic do_next,
     output logic Finish,
     output logic RESET_cmd,
     output logic Load_op,
@@ -11,9 +12,12 @@ module CONTROLLER_MAC (
 );
 
     logic [3:0] temp_count;
-    enum logic [2:0] {IDLE, INIT, LOAD, RUN, TEST, ADD} state;
+    enum logic [2:0] {IDLE, INIT, LOAD, RUN, TEST, ADD, WAIT} state;
 
+    logic _do_next;
     always_ff @(posedge clk) begin
+        _do_next <= do_next;
+
         if (!reset) begin
             state      <= IDLE;
             temp_count <= 4'b1001;
@@ -51,6 +55,11 @@ module CONTROLLER_MAC (
                         state      <= IDLE;
                     end
                     else begin
+                        state <= WAIT;
+                    end
+                end
+                WAIT: begin
+                    if (do_next && !_do_next) begin
                         temp_count <= temp_count - 1;
                         state      <= LOAD;
                     end

designs/d18_nikhildj_mac/test_wrapped.sv

@@ -0,0 +1,89 @@
+module test;
+
+    logic reset, clock;
+    logic mac_carry_out, finish, shiftout, end_mul;
+    logic [11:0] io_out;
+    logic start, shiftA, shiftB, shift, do_next;
+
+    assign {mac_carry_out, finish, shiftout, end_mul} = io_out[11:8];
+
+    my_chip dut (
+        .clock(clock),
+        .reset(reset),
+        .io_in({start, shiftA, shiftB, shift, do_next, 7'b0}),
+        .io_out(io_out)
+    );
+
+    initial begin
+        clock = 0;
+        forever #5 clock = ~clock;
+    end
+
+    task shiftIn (input [7:0] d1, input [7:0] d2);
+        begin
+            for (int i = 0; i < 8; i += 1) begin
+                shiftA = d1[7-i]; shiftB = d2[7-i];
+                shift = 1; @(posedge clock); @(posedge clock);
+                shift = 0; @(posedge clock); @(posedge clock);
+            end
+
+        end
+    endtask
+
+    logic [19:0] dout;
+    task shiftOut ();
+        begin
+            for (int i = 0; i < 20; i += 1) begin
+                dout[i] = shiftout;
+                shift = 1; @(posedge clock); @(posedge clock);
+                shift = 0; @(posedge clock); @(posedge clock);
+            end
+
+        end
+    endtask
+
+    initial begin
+        reset = 1;
+        start = 0;
+        shiftA = 0;
+        shiftB = 0;
+        shift = 0;
+        do_next = 0;
+
+        $monitor($time,, "finish=%d, end_mul=%d, shiftout=%d, start=%d, shiftA=%d, shiftB=%d, shift=%d",
+            finish, end_mul, shiftout, start, shiftA, shiftB, shift);
+
+        @(posedge clock)
+        @(posedge clock)
+        reset = 0;
+        @(posedge clock)
+        @(posedge clock)
+
+
+        start = 1;
+        @(posedge clock);
+        start = 0;
+        @(posedge clock);
+        @(posedge clock);
+
+        repeat(100) @(posedge clock);
+
+        for (int i = 0; i < 9; i++) begin
+            shiftIn(i+2, i+3);
+            repeat(20) @(posedge clock);
+            do_next = 1;
+            @(posedge clock)
+            do_next = 0;
+            repeat(100) @(posedge clock);
+        end
+
+        while (!finish) @(posedge clock);
+        @(posedge clock);
+        @(posedge clock);
+        shiftOut();
+        $display("result = %d (exp = 438)", dout);
+
+        $finish;
+    end
+
+endmodule