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1 change: 1 addition & 0 deletions designs/.lastupdated
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2023-05-14
1 change: 1 addition & 0 deletions designs/d10_wabib_tictactoe/.lastupdated
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2023-05-14
201 changes: 201 additions & 0 deletions designs/d10_wabib_tictactoe/LICENSE
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26 changes: 26 additions & 0 deletions designs/d10_wabib_tictactoe/README.md
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# Tic-Tac-Toe

Wahib Abib
18-224/624 Spring 2023 Final Tapeout Project

## Overview

The classic game of Tic-Tac-Toe on an ASIC, with a built in game AI if the user wants to play by themselves. The chip also supports 2 players competing agasint each other.

## How it Works

The user will first select how many players the game will have by flipping the on-board switch. The user can select what move they would like to make on the Tic-Tac-Toe board by pressing the buttons on the game board. If the move is invalid, the position was already selected, then the user has to select another move. During 1-player mode, the AI will select its move which will be displayed on the game board. During 2-player mode, the next player will be allowed to make their next move. When there is a winner, the game board will reset and and the user will have to press the start button the start a new game.

## Inputs/Outputs

The chip uses an external clock input at 2MHz

9 of the inputs are used for the 9 positions on the tic tac toe board (b0-b8) which are driven by the on-board buttons, 1 input is for selecting 1 or 2 player mode (player_sel), and 1 input is to start the game (start). 9 of the outputs are used to drive onboard LEDs to display the player’s move (led0-led8).

## Hardware Peripherals

There will be 9 on-board buttons for each possible move, 9 on-board LED's to display the current game board, and 1 on-board switch to select the number of players

## Design Testing / Bringup

Once the game board is constructed, the chip can be tested by simply pressing the start button and pressing the on-board positions buttons to see if the move was registered and displayed.
7 changes: 7 additions & 0 deletions designs/d10_wabib_tictactoe/info.yaml
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---
project:
source_files:
- toplevel_chip.v
- chip.sv
- ttt.sv
top_module: "toplevel_chip"
35 changes: 35 additions & 0 deletions designs/d10_wabib_tictactoe/src/chip.sv
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`default_nettype none

module my_chip (
input logic [11:0] io_in, // Inputs to your chip
output logic [11:0] io_out, // Outputs from your chip
input logic clock,
input logic reset // Important: Reset is ACTIVE-HIGH
);

ttt_game_control ttt(.b0(io_in[0]),
.b1(io_in[1]),
.b2(io_in[2]),
.b3(io_in[3]),
.b4(io_in[4]),
.b5(io_in[5]),
.b6(io_in[6]),
.b7(io_in[7]),
.b8(io_in[8]),
.player_sel(io_in[9]),
.start(io_in[10]),
.led0(io_out[0]),
.led1(io_out[1]),
.led2(io_out[2]),
.led3(io_out[3]),
.led4(io_out[4]),
.led5(io_out[5]),
.led6(io_out[6]),
.led7(io_out[7]),
.led8(io_out[8]),
.clk(clock),
.reset(reset));

assign io_out[11:9] = 3'd0;

endmodule
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# PLEASE DO NOT EDIT THIS FILE!
# IT WILL MAKE YOUR CHIP UNMANUFACTURABLE
# The only line you may edit is FP_CORE_UTIL
# (may benefit from reducing it slightly)

# User config
set script_dir [file dirname [file normalize [info script]]]

# read some user config that is written by the setup.py program.
# - the name of the module is defined
# - the list of source files
source $::env(DESIGN_DIR)/user_config.tcl

# save some time
set ::env(RUN_KLAYOUT_XOR) 0
set ::env(RUN_KLAYOUT_DRC) 0

# don't put clock buffers on the outputs
set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0

# allow use of specific sky130 cells
set ::env(SYNTH_READ_BLACKBOX_LIB) 1

# put all the pins on the left
set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg

# reduce wasted space
set ::env(TOP_MARGIN_MULT) 2
set ::env(BOTTOM_MARGIN_MULT) 2

# absolute die size
set ::env(FP_SIZING) absolute
set ::env(DIE_AREA) "0 0 280 280"

## THIS IS THE ONLY LINE YOU CAN EDIT
set ::env(FP_CORE_UTIL) 45

## set ::env(PL_BASIC_PLACEMENT) {1}

set ::env(FP_IO_HLENGTH) 2
set ::env(FP_IO_VLENGTH) 2

# use alternative efabless decap cells to solve LI density issue
set ::env(DECAP_CELL) "\
sky130_fd_sc_hd__decap_3 \
sky130_fd_sc_hd__decap_4 \
sky130_fd_sc_hd__decap_6 \
sky130_fd_sc_hd__decap_8 \
sky130_ef_sc_hd__decap_12"

# clock
set ::env(CLOCK_TREE_SYNTH) 1

# period is in ns, so 500ns == 2 MHz
set ::env(CLOCK_PERIOD) "500"
set ::env(CLOCK_PORT) {io_in[12]}

# hold/slack margin
# set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) 0.8
# set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) 0.8

# don't use power rings or met5
set ::env(DESIGN_IS_CORE) 0
set ::env(RT_MAX_LAYER) {met4}

# connect to first digital rails
set ::env(VDD_NETS) [list {vccd1}]
set ::env(GND_NETS) [list {vssd1}]
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#N

#S

#E

#W
io_in.*
io_out.*
18 changes: 18 additions & 0 deletions designs/d10_wabib_tictactoe/src/toplevel_chip.v
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`default_nettype none

// DO NOT EDIT THIS FILE
module toplevel_chip (
input [13:0] io_in,
output [13:0] io_out
);

my_chip mchip (
.io_in(io_in[11:0]),
.io_out(io_out[11:0]),
.clock(io_in[12]),
.reset(io_in[13])
);

assign io_out[13:12] = 2'b00;

endmodule
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