rockchip64-6.14: Add missing opp nodes

[SuperKali]

Description

This PR adds missing Operating Performance Point (OPP) nodes for lower frequencies to the RK3588 device tree. by enabling the CPU clusters to scale down to lower frequencies when under light loads.

The changes add OPP nodes for 408MHz, 600MHz, 816MHz, and 1008MHz (for cluster1 and cluster2 only, as cluster0 already had 1008MHz).

How Has This Been Tested?

• Tested with RK3588-based board (NanoPC T6-LTS) and verified CPU frequency scaling works correctly

Checklist:

• My code follows the style guidelines of this project
• I have performed a self-review of my own code
• My changes generate no new warnings

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[amazingfate]

Is it possible to send it upstream?

[SuperKali]

Is it possible to send it upstream?

Definitely yes, but I don't have the technical knowledge to send it upstream, hopefully someone will explain it to me someday, or else I'll have to figure it out myself.

[SuperKali]

@amazingfate i tried to send it on mainline, definitely I was wrong to put two email addresses but it should be no problem, let's see what happens.

[SuperKali]

WIP: I was informed by mainline developers that frequency scaling alone doesn't provide effective power savings without corresponding voltage reduction. I'm currently researching the RK3588 datasheet to determine the minimum safe voltage levels for each frequency step and will propose a revised patch with properly tested voltage scaling.

[SuperKali]

After carefully reviewing the RK3588 datasheet again, I've found that the typical recommended voltage values are always higher than what I had configured in my patch. Since this PR only implements frequency scaling without proper voltage reduction, it doesn't actually save energy.

The datasheet's typical values are there for a reason - they ensure stable operation across all silicon variants and operating conditions. Without proper voltage scaling (which would require extensive testing to validate stable operation at lower voltages), simply adding lower frequency steps doesn't provide meaningful power savings.

Given these findings, I'm closing this PR.

[paolosabatino]

After carefully reviewing the RK3588 datasheet again, I've found that the typical recommended voltage values are always higher than what I had configured in my patch. Since this PR only implements frequency scaling without proper voltage reduction, it doesn't actually save energy.

AFAIK this is not entirely true.

Power consumption has a linear dependency against frequency and quadratic dependency against voltage. The assertion of the mainline developer cited above is not formally correct.

This is the answer from chatgpt to the question: how does the power consumption of a chip depends against frequency and against voltage?

So voltage has the capacity to decrease the power consumption of a wide amount, but also frequency has its own capacity. What the mainline kernel developer was probably talking about is that lowering the frequency too much when the chip is idle, decreases the power consumption in a trascurable manner: that could be indeed be true.

But there is another variable in the game: thermal throttling! If your chip is thermally throrrling, having a lower speed bin may decrease a lot the power consumption in a thermally constrained condition. For example: keeping the voltage fixed, if your chip at full load consumes (and dissipates) 2 watts at 2ghz, will consume (and dissipate) 1 watt at 1ghz and will consume 0.6watts at 600mhz.

Another thing to consider is frequencies that are too low will reduce the promptness of the processor. Usually 408Mhz speed bin is discarded for this reason, for example.

[SuperKali]

@paolosabatino So what would you say to do? :)

To make it easier for you, I leave you the link to the patch posted in the mainline: https://lore.kernel.org/all/[email protected]/T/

Be patient it is my first mainline patch, don't criticize me.