This project implements a simple 8-bit soft-core processor using a Finite State Machine (FSM) model. The processor consists of various key modules such as the Arithmetic Logic Unit (ALU), Program Memory (PMem), Data Memory (DMem), and a series of control logic components. The Control_Logic module plays a crucial role in generating control signals based on the current state and instruction type, facilitating the execution of a set of basic operations.
The processor follows a sequence of states—LOAD, FETCH, DECODE, and EXECUTE—to process instructions stored in program memory. This design demonstrates fundamental concepts of computer architecture and digital design using Verilog HDL for FPGA implementation.
- 8-bit Architecture: Designed for efficient implementation on FPGAs
- FSM-Based Control: Uses a four-state finite state machine for instruction execution
- Modular Design: Well-structured Verilog modules for easy understanding and modification
- Comprehensive ALU: Supports arithmetic, logical, and shift operations
- Separate Memory Units: Dedicated program and data memory spaces
- Simulation Ready: Includes testbench for functional verification
- FPGA Synthesizable: Compatible with major FPGA development tools
├── Project.v # Main processor module and submodules
├── testbench.v # Testbench for simulation
├── progr.dat # Sample program instructions file
├── README.md # This file
└── LICENSE.txt # MIT License
The processor operates using a state-based approach, transitioning through the following states:
- LOAD: Initializes the processor by loading the program into memory
- FETCH: Fetches instructions from Program Memory based on the Program Counter (PC)
- DECODE: Decodes the fetched instruction and prepares the necessary control signals
- EXECUTE: Executes the instruction using the ALU and updates the relevant registers
RESET
↓
LOAD → FETCH → DECODE → EXECUTE
↑ ↓
←--------------------
[Program Memory] → [Instruction Register] → [Control Logic] → [ALU/Data Memory]
↑ ↓
[Program Counter] ← [Adder/MUX] ← [Control Signals] ← [Status Register]
The processor uses 12-bit instructions with multiple formats depending on the operation type. Here are the supported instruction types:
These instructions perform ALU operations with an immediate value:
| Bits [10:8] | Operation | Description |
|---|---|---|
| 000 | ADD | Acc = Acc + Immediate |
| 001 | SUB | Acc = Acc - Immediate |
| 010 | MOV A, Acc | Acc = Acc (no change) |
| 011 | MOV A, Imm | Acc = Immediate |
| 100 | AND | Acc = Acc & Immediate |
| 101 | OR | Acc = Acc |
| 110 | XOR | Acc = Acc ^ Immediate |
| 111 | SUBR | Acc = Immediate - Acc |
These instructions interact with data memory:
- When IR[8] = 0: Read from data memory address IR[3:0] to Data Register
- When IR[8] = 1: Write accumulator value to data memory address IR[3:0]
Conditional jumps based on status flags:
- JZ (Jump if Zero): IR[9:8] = 00
- JC (Jump if Carry): IR[9:8] = 01
- JS (Jump if Sign): IR[9:8] = 10
- JO (Jump if Overflow): IR[9:8] = 11
Instructions that don't match the above patterns simply increment the program counter.
The provided progr.dat file contains a sample program that demonstrates basic operations:
000000000000 // NOP - No operation, just increment PC
101100000001 // MOV A, #1 - Load immediate value 1 into accumulator
001000100000 // LOAD [0] - Load value from data memory address 0 to DR
101100000000 // MOV A, #0 - Load immediate value 0 into accumulator
001100110000 // STORE Acc to [0] - Store accumulator to data memory address 0
000100000101 // NOP - No operation, just increment PC
000000000000 // NOP
000000000000 // NOP
000000000000 // NOP
000000000000 // NOP
The central module orchestrating the processor's functionality by defining and managing the state transitions. It coordinates the interaction between Program Memory, Data Memory, ALU, and Control Logic, ensuring seamless execution of instructions.
Key components:
- State management (LOAD, FETCH, DECODE, EXECUTE)
- Register file (PC, Acc, SR, DR, IR)
- Control signal generation
- Data path management
Generates the necessary control signals to operate the processor's components based on the current state and the decoded instruction. It drives the behavior of registers, memory units, ALU, and multiplexers.
Stores instructions and provides a mechanism to load instructions into memory using external files. The memory is initialized with program instructions during the LOAD state.
Handles data storage and retrieval during program execution. Supports read and write operations controlled by enable signals.
Implements various arithmetic and logical operations. The ALU is responsible for performing core computations within the processor, supporting operations such as:
- Addition and subtraction
- Bitwise AND, OR, XOR
- Logical and arithmetic shifts
- Increment and decrement
- Two's complement negation
Implement data selection for various operations within the processor, choosing between different data sources based on control signals.
Performs simple addition, used primarily for incrementing the Program Counter.
- Program Counter (PC): Tracks the address of the next instruction (8-bit)
- Accumulator (Acc): Stores results of arithmetic and logic operations (8-bit)
- Status Register (SR): Holds status flags such as zero, carry, sign, and overflow (4-bit)
- SR[3]: Zero flag (Z)
- SR[2]: Carry flag (C)
- SR[1]: Sign flag (S)
- SR[0]: Overflow flag (O)
- Data Register (DR): Temporarily holds data during execution (8-bit)
- Instruction Register (IR): Stores the currently fetched instruction (12-bit)
The ALU supports a variety of operations controlled by a 4-bit mode input:
| Mode | Operation | Description |
|---|---|---|
| 0000 | ADD | Addition |
| 0001 | SUB | Subtraction |
| 0010 | MOV A, Operand1 | Move first operand to Acc |
| 0011 | MOV A, Operand2 | Move second operand to Acc |
| 0100 | AND | Bitwise AND |
| 0101 | OR | Bitwise OR |
| 0110 | XOR | Bitwise XOR |
| 0111 | SUBR | Reverse subtraction |
| 1000 | INC | Increment second operand |
| 1001 | DEC | Decrement second operand |
| 1010 | ROL | Rotate left |
| 1011 | ROR | Rotate right |
| 1100 | SHL | Shift left |
| 1101 | SHR | Shift right |
| 1110 | ASHR | Arithmetic shift right |
| 1111 | NEG | Two's complement negation |
The processor utilizes Program Memory (PMem) to store instructions and Data Memory (DMem) to store data. Instructions are loaded into PMem during the LOAD state, while DMem handles data read and write operations during program execution.
Instructions are loaded from an external file (progr.dat) during initialization. The format of this file should match the 12-bit instruction format expected by the processor.
To simulate and test this processor, you'll need:
- Icarus Verilog - Open source Verilog simulation and synthesis tool
- GTKWave - Open source waveform viewer (optional but recommended)
- Text editor - For viewing and modifying Verilog files
Alternatively, you can use commercial tools like:
- Xilinx Vivado
- Intel Quartus
- ModelSim
-
Install Icarus Verilog:
# Ubuntu/Debian sudo apt-get install iverilog gtkwave # macOS (using Homebrew) brew install icarus-verilog # Windows (using Chocolatey) choco install icarusverilog
-
Clone or download this repository:
git clone <repository-url> cd 8BitMicroFPGA
-
Compile the design with the testbench:
iverilog -o processor.out Project.v testbench.v
-
Run the simulation:
./processor.out
-
To view waveforms, modify the testbench to include waveform dumping:
module testbench; // Inputs reg clk; reg rst; // Instantiate the Unit Under Test (UUT) Project uut ( .clk(clk), .rst(rst) ); initial begin // Initialize Inputs rst = 1; // Wait 100 ns for global reset to finish #100; rst = 0; // Dump waves for debugging $dumpfile("processor.vcd"); $dumpvars(0, testbench); // Run simulation for specific time #1000 $finish; end initial begin clk = 0; forever #10 clk = ~clk; end endmodule
-
Then compile and run again:
iverilog -o processor.out Project.v testbench.v ./processor.out gtkwave processor.vcd
To create your own program:
- Edit the progr.dat file with your 12-bit binary instructions
- Each line represents one instruction in binary format
- The processor supports up to 10 instructions (addresses 0-9)
Example program that adds two numbers:
101100000010 // MOV A, #2 (Load 2 into accumulator)
001000000001 // ADD [1] (Add value from data memory address 1)
000000000000 // NOP
000000000000 // NOP
000000000000 // NOP
000000000000 // NOP
000000000000 // NOP
000000000000 // NOP
000000000000 // NOP
000000000000 // NOP
Before running this program, you would need to initialize data memory location 1 with a value.
The processor design has been simulated and tested using testbenches to verify its correct operation. The modular approach facilitates easy testing of individual components as well as the overall processor.
The included testbench.v file provides a basic testing framework that:
- Resets the processor
- Provides clock signals
- Allows observation of internal signals
For more comprehensive testing, you can extend the testbench to:
- Monitor specific signals
- Add assertions for expected behavior
- Generate test vectors
- Automate regression testing
To properly analyze the processor behavior:
- Modify the testbench to include waveform dumping as shown in the "Running the Simulation" section
- Run the simulation
- Open the VCD file with GTKWave:
gtkwave processor.vcd
In GTKWave, you can observe:
- Clock and reset signals
- Current state of the FSM
- Register values (PC, Acc, SR, DR, IR)
- Control signals
- Memory contents
Contributions are welcome! Here are some ways you can contribute:
- Bug Reports: If you find any issues, please open an issue with a detailed description
- Feature Requests: Suggest enhancements or new features
- Code Improvements: Submit pull requests with optimizations or bug fixes
- Documentation: Help improve this README or add comments to the code
- Testing: Add more comprehensive test cases
- Additional Instructions: Implement more instructions for the ISA
Before submitting a pull request:
- Ensure your code follows Verilog best practices
- Test your changes thoroughly
- Update documentation as needed
- Keep changes focused and well-described
This project is licensed under the MIT License - see the LICENSE.txt file for details.
MIT License
Copyright (c) 2024 Malik Mohammad Ammar
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
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The above copyright notice and this permission notice shall be included in all
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
For questions, suggestions, or feedback, please open an issue on the GitHub repository.
This repository contains all the necessary Verilog code and supporting files to synthesize the 8-bit soft-core processor on an FPGA. The code is well-commented, following best practices in digital design to ensure clarity and maintainability.