feat: add prover support for LR/SC atomic instructions #1227
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Implement RISCVTrace with inline_sequence for LR.W, LR.D, SC.W, and SC.D instructions. Reserve virtual register 32 for storing the reservation address, enabling proper constraint generation for atomic operations. - Add reservation_register() to VirtualRegisterAllocator (register 32) - Update allocate() and allocate_for_inline() to skip reserved register - LR.W/LR.D: Store reservation address in v_reservation, then load - SC.W/SC.D: Assert reservation matches, store value, clear reservation
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Implement RISCVTrace with inline_sequence for LR.W, LR.D, SC.W, and SC.D instructions. Reserve virtual register 32 for storing the reservation address, enabling proper constraint generation for atomic operations.