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s/NEW_ID/NEWER_ID/g
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130 files changed

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‎backends/aiger2/aiger.cc‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1040,7 +1040,7 @@ struct XAigerWriter : AigerWriter {
10401040
for (auto [cursor, box, def] : opaque_boxes)
10411041
append_box_ports(box, cursor, false);
10421042

1043-
holes_module = design->addModule(NEW_ID);
1043+
holes_module = design->addModule(NEWER_ID);
10441044
std::vector<RTLIL::Wire *> holes_pis;
10451045
int boxes_ci_num = 0, boxes_co_num = 0;
10461046

@@ -1058,7 +1058,7 @@ struct XAigerWriter : AigerWriter {
10581058

10591059
for (auto [cursor, box, def] : nonopaque_boxes) {
10601060
// use `def->name` not `box->type` as we want the derived type
1061-
Cell *holes_wb = holes_module->addCell(NEW_ID, def->name);
1061+
Cell *holes_wb = holes_module->addCell(NEWER_ID, def->name);
10621062
int holes_pi_idx = 0;
10631063

10641064
if (map_file.is_open()) {
@@ -1097,7 +1097,7 @@ struct XAigerWriter : AigerWriter {
10971097
SigSpec in_conn;
10981098
for (int i = 0; i < port->width; i++) {
10991099
while (holes_pi_idx >= (int) holes_pis.size()) {
1100-
Wire *w = holes_module->addWire(NEW_ID, 1);
1100+
Wire *w = holes_module->addWire(NEWER_ID, 1);
11011101
w->port_input = true;
11021102
holes_module->ports.push_back(w->name);
11031103
holes_pis.push_back(w);
@@ -1126,7 +1126,7 @@ struct XAigerWriter : AigerWriter {
11261126
boxes_ci_num += port->width;
11271127

11281128
// holes
1129-
Wire *w = holes_module->addWire(NEW_ID, port->width);
1129+
Wire *w = holes_module->addWire(NEWER_ID, port->width);
11301130
w->port_output = true;
11311131
holes_module->ports.push_back(w->name);
11321132
holes_wb->setPort(port_id, w);

‎backends/verilog/verilog_backend.cc‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2372,7 +2372,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
23722372
}
23732373
f << stringf(");\n");
23742374
if (!systemverilog && !module->processes.empty()) {
2375-
initial_id = NEW_ID;
2375+
initial_id = NEWER_ID;
23762376
f << indent + " " << "reg " << id(initial_id) << " = 0;\n";
23772377
}
23782378

‎docs/source/code_examples/extensions/my_cmd.cc‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -38,9 +38,9 @@ struct Test1Pass : public Pass {
3838
y->port_output = true;
3939
y->port_id = 2;
4040

41-
RTLIL::Wire *a_inv = module->addWire(NEW_ID, 4);
42-
module->addNeg(NEW_ID, a, a_inv, true);
43-
module->addMux(NEW_ID, a, a_inv, RTLIL::SigSpec(a, 3), y);
41+
RTLIL::Wire *a_inv = module->addWire(NEWER_ID, 4);
42+
module->addNeg(NEWER_ID, a, a_inv, true);
43+
module->addMux(NEWER_ID, a, a_inv, RTLIL::SigSpec(a, 3), y);
4444

4545
module->fixup_ports();
4646
}

‎frontends/aiger/aigerparse.cc‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -559,9 +559,9 @@ void AigerReader::parse_aiger_ascii()
559559
RTLIL::Wire *d_wire = createWireIfNotExists(module, l2);
560560

561561
if (clk_wire)
562-
module->addDffGate(NEW_ID, clk_wire, d_wire, q_wire);
562+
module->addDffGate(NEWER_ID, clk_wire, d_wire, q_wire);
563563
else
564-
module->addFfGate(NEW_ID, d_wire, q_wire);
564+
module->addFfGate(NEWER_ID, d_wire, q_wire);
565565

566566
// Reset logic is optional in AIGER 1.9
567567
if (f.peek() == ' ') {
@@ -683,9 +683,9 @@ void AigerReader::parse_aiger_binary()
683683
RTLIL::Wire *d_wire = createWireIfNotExists(module, l2);
684684

685685
if (clk_wire)
686-
module->addDff(NEW_ID, clk_wire, d_wire, q_wire);
686+
module->addDff(NEWER_ID, clk_wire, d_wire, q_wire);
687687
else
688-
module->addFf(NEW_ID, d_wire, q_wire);
688+
module->addFf(NEWER_ID, d_wire, q_wire);
689689

690690
// Reset logic is optional in AIGER 1.9
691691
if (f.peek() == ' ') {
@@ -795,7 +795,7 @@ void AigerReader::post_process()
795795
log_assert(q->port_input);
796796
q->port_input = false;
797797

798-
Cell* ff = module->addFfGate(NEW_ID, d, q);
798+
Cell* ff = module->addFfGate(NEWER_ID, d, q);
799799
ff->attributes[ID::abc9_mergeability] = mergeability[i];
800800
q->attributes[ID::init] = initial_state[i];
801801
}

‎frontends/ast/genrtlil.cc‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -822,7 +822,7 @@ struct AST_INTERNAL::ProcessGenerator
822822

823823
RTLIL::SigSpec check = ast->children[0]->genWidthRTLIL(-1, false, &subst_rvalue_map.stdmap());
824824
if (GetSize(check) != 1)
825-
check = current_module->ReduceBool(NEW_ID, check);
825+
check = current_module->ReduceBool(NEWER_ID, check);
826826

827827
Wire *en = current_module->addWire(cellname.str() + "_EN", 1);
828828
set_src_attr(en, ast);
@@ -1626,11 +1626,11 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
16261626
RTLIL::SigSpec shift_val = fake_ast->children[1]->genRTLIL(fake_ast_width, fake_ast_sign);
16271627

16281628
if (source_offset != 0) {
1629-
shift_val = current_module->Sub(NEW_ID, shift_val, source_offset, fake_ast_sign);
1629+
shift_val = current_module->Sub(NEWER_ID, shift_val, source_offset, fake_ast_sign);
16301630
fake_ast->children[1]->is_signed = true;
16311631
}
16321632
if (id2ast->range_swapped) {
1633-
shift_val = current_module->Sub(NEW_ID, RTLIL::SigSpec(source_width - width), shift_val, fake_ast_sign);
1633+
shift_val = current_module->Sub(NEWER_ID, RTLIL::SigSpec(source_width - width), shift_val, fake_ast_sign);
16341634
fake_ast->children[1]->is_signed = true;
16351635
}
16361636
if (GetSize(shift_val) >= 32)
@@ -2028,7 +2028,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
20282028

20292029
RTLIL::SigSpec check = children[0]->genRTLIL();
20302030
if (GetSize(check) != 1)
2031-
check = current_module->ReduceBool(NEW_ID, check);
2031+
check = current_module->ReduceBool(NEWER_ID, check);
20322032

20332033
RTLIL::Cell *cell = current_module->addCell(cellname, ID($check));
20342034
set_src_attr(cell, this);
@@ -2130,7 +2130,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
21302130
} else if (arg->is_signed) {
21312131
// non-trivial signed nodes are indirected through
21322132
// signed wires to enable sign extension
2133-
RTLIL::IdString wire_name = NEW_ID;
2133+
RTLIL::IdString wire_name = NEWER_ID;
21342134
RTLIL::Wire *wire = current_module->addWire(wire_name, GetSize(sig));
21352135
wire->is_signed = true;
21362136
current_module->connect(wire, sig);

‎frontends/blif/blifparse.cc‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -363,19 +363,19 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
363363
goto no_latch_clock;
364364

365365
if (!strcmp(edge, "re"))
366-
cell = module->addDff(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q));
366+
cell = module->addDff(NEWER_ID, blif_wire(clock), blif_wire(d), blif_wire(q));
367367
else if (!strcmp(edge, "fe"))
368-
cell = module->addDff(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false);
368+
cell = module->addDff(NEWER_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false);
369369
else if (!strcmp(edge, "ah"))
370-
cell = module->addDlatch(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q));
370+
cell = module->addDlatch(NEWER_ID, blif_wire(clock), blif_wire(d), blif_wire(q));
371371
else if (!strcmp(edge, "al"))
372-
cell = module->addDlatch(NEW_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false);
372+
cell = module->addDlatch(NEWER_ID, blif_wire(clock), blif_wire(d), blif_wire(q), false);
373373
else {
374374
no_latch_clock:
375375
if (dff_name.empty()) {
376-
cell = module->addFf(NEW_ID, blif_wire(d), blif_wire(q));
376+
cell = module->addFf(NEWER_ID, blif_wire(d), blif_wire(q));
377377
} else {
378-
cell = module->addCell(NEW_ID, dff_name);
378+
cell = module->addCell(NEWER_ID, dff_name);
379379
cell->setPort(ID::D, blif_wire(d));
380380
cell->setPort(ID::Q, blif_wire(q));
381381
}
@@ -394,7 +394,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
394394
goto error;
395395

396396
IdString celltype = RTLIL::escape_id(p);
397-
RTLIL::Cell *cell = module->addCell(NEW_ID, celltype);
397+
RTLIL::Cell *cell = module->addCell(NEWER_ID, celltype);
398398
RTLIL::Module *cell_mod = design->module(celltype);
399399

400400
dict<RTLIL::IdString, dict<int, SigBit>> cell_wideports_cache;
@@ -441,7 +441,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
441441
if (it.second.count(idx))
442442
sig.append(it.second.at(idx));
443443
else
444-
sig.append(module->addWire(NEW_ID));
444+
sig.append(module->addWire(NEWER_ID));
445445
}
446446

447447
cell->setPort(it.first, sig);
@@ -517,7 +517,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
517517

518518
if (sop_mode)
519519
{
520-
sopcell = module->addCell(NEW_ID, ID($sop));
520+
sopcell = module->addCell(NEWER_ID, ID($sop));
521521
sopcell->parameters[ID::WIDTH] = RTLIL::Const(input_sig.size());
522522
sopcell->parameters[ID::DEPTH] = 0;
523523
sopcell->parameters[ID::TABLE] = RTLIL::Const();
@@ -533,7 +533,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
533533
}
534534
else
535535
{
536-
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($lut));
536+
RTLIL::Cell *cell = module->addCell(NEWER_ID, ID($lut));
537537
cell->parameters[ID::WIDTH] = RTLIL::Const(input_sig.size());
538538
cell->parameters[ID::LUT] = RTLIL::Const(RTLIL::State::Sx, 1 << input_sig.size());
539539
cell->setPort(ID::A, input_sig);
@@ -586,8 +586,8 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool
586586
sopmode = (*output == '1');
587587
if (!sopmode) {
588588
SigSpec outnet = sopcell->getPort(ID::Y);
589-
SigSpec tempnet = module->addWire(NEW_ID);
590-
module->addNotGate(NEW_ID, tempnet, outnet);
589+
SigSpec tempnet = module->addWire(NEWER_ID);
590+
module->addNotGate(NEWER_ID, tempnet, outnet);
591591
sopcell->setPort(ID::Y, tempnet);
592592
}
593593
} else

‎frontends/json/jsonparse.cc‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -549,7 +549,7 @@ void json_import(Design *design, string &modname, JsonNode *node)
549549
if (bitval_node->type == 'N') {
550550
int bitidx = bitval_node->data_number;
551551
if (signal_bits.count(bitidx) == 0)
552-
signal_bits[bitidx] = module->addWire(NEW_ID);
552+
signal_bits[bitidx] = module->addWire(NEWER_ID);
553553
sig.append(signal_bits.at(bitidx));
554554
} else
555555
log_error("JSON cells node '%s' connection '%s' has invalid bit value on bit %d.\n",

‎frontends/liberty/liberty.cc‎

Lines changed: 26 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -58,15 +58,15 @@ static bool parse_func_reduce(RTLIL::Module *module, std::vector<token_t> &stack
5858
int top = int(stack.size())-1;
5959

6060
if (0 <= top-1 && stack[top].type == 0 && stack[top-1].type == '!') {
61-
token_t t = token_t(0, module->NotGate(NEW_ID, stack[top].sig));
61+
token_t t = token_t(0, module->NotGate(NEWER_ID, stack[top].sig));
6262
stack.pop_back();
6363
stack.pop_back();
6464
stack.push_back(t);
6565
return true;
6666
}
6767

6868
if (0 <= top-1 && stack[top].type == '\'' && stack[top-1].type == 0) {
69-
token_t t = token_t(0, module->NotGate(NEW_ID, stack[top-1].sig));
69+
token_t t = token_t(0, module->NotGate(NEWER_ID, stack[top-1].sig));
7070
stack.pop_back();
7171
stack.pop_back();
7272
stack.push_back(t);
@@ -81,7 +81,7 @@ static bool parse_func_reduce(RTLIL::Module *module, std::vector<token_t> &stack
8181
}
8282

8383
if (0 <= top-2 && stack[top-2].type == 1 && stack[top-1].type == '^' && stack[top].type == 1) {
84-
token_t t = token_t(1, module->XorGate(NEW_ID, stack[top-2].sig, stack[top].sig));
84+
token_t t = token_t(1, module->XorGate(NEWER_ID, stack[top-2].sig, stack[top].sig));
8585
stack.pop_back();
8686
stack.pop_back();
8787
stack.pop_back();
@@ -97,15 +97,15 @@ static bool parse_func_reduce(RTLIL::Module *module, std::vector<token_t> &stack
9797
}
9898

9999
if (0 <= top-1 && stack[top-1].type == 2 && stack[top].type == 2) {
100-
token_t t = token_t(2, module->AndGate(NEW_ID, stack[top-1].sig, stack[top].sig));
100+
token_t t = token_t(2, module->AndGate(NEWER_ID, stack[top-1].sig, stack[top].sig));
101101
stack.pop_back();
102102
stack.pop_back();
103103
stack.push_back(t);
104104
return true;
105105
}
106106

107107
if (0 <= top-2 && stack[top-2].type == 2 && (stack[top-1].type == '*' || stack[top-1].type == '&') && stack[top].type == 2) {
108-
token_t t = token_t(2, module->AndGate(NEW_ID, stack[top-2].sig, stack[top].sig));
108+
token_t t = token_t(2, module->AndGate(NEWER_ID, stack[top-2].sig, stack[top].sig));
109109
stack.pop_back();
110110
stack.pop_back();
111111
stack.pop_back();
@@ -121,7 +121,7 @@ static bool parse_func_reduce(RTLIL::Module *module, std::vector<token_t> &stack
121121
}
122122

123123
if (0 <= top-2 && stack[top-2].type == 3 && (stack[top-1].type == '+' || stack[top-1].type == '|') && stack[top].type == 3) {
124-
token_t t = token_t(3, module->OrGate(NEW_ID, stack[top-2].sig, stack[top].sig));
124+
token_t t = token_t(3, module->OrGate(NEWER_ID, stack[top-2].sig, stack[top].sig));
125125
stack.pop_back();
126126
stack.pop_back();
127127
stack.pop_back();
@@ -183,11 +183,11 @@ static RTLIL::SigSpec create_tristate(RTLIL::Module *module, RTLIL::SigSpec func
183183
{
184184
RTLIL::SigSpec three_state = parse_func_expr(module, three_state_expr);
185185

186-
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($tribuf));
186+
RTLIL::Cell *cell = module->addCell(NEWER_ID, ID($tribuf));
187187
cell->setParam(ID::WIDTH, GetSize(func));
188188
cell->setPort(ID::A, func);
189-
cell->setPort(ID::EN, module->NotGate(NEW_ID, three_state));
190-
cell->setPort(ID::Y, module->addWire(NEW_ID));
189+
cell->setPort(ID::EN, module->NotGate(NEWER_ID, three_state));
190+
cell->setPort(ID::Y, module->addWire(NEWER_ID));
191191
return cell->getPort(ID::Y);
192192
}
193193

@@ -236,11 +236,11 @@ static void create_ff(RTLIL::Module *module, const LibertyAst *node)
236236
}
237237
}
238238

239-
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_NOT_));
239+
RTLIL::Cell *cell = module->addCell(NEWER_ID, ID($_NOT_));
240240
cell->setPort(ID::A, iq_sig);
241241
cell->setPort(ID::Y, iqn_sig);
242242

243-
cell = module->addCell(NEW_ID, "");
243+
cell = module->addCell(NEWER_ID, "");
244244
cell->setPort(ID::D, data_sig);
245245
cell->setPort(ID::Q, iq_sig);
246246
cell->setPort(ID::C, clk_sig);
@@ -319,7 +319,7 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla
319319
}
320320
}
321321

322-
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_NOT_));
322+
RTLIL::Cell *cell = module->addCell(NEWER_ID, ID($_NOT_));
323323
cell->setPort(ID::A, iq_sig);
324324
cell->setPort(ID::Y, iqn_sig);
325325

@@ -330,25 +330,25 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla
330330

331331
if (clear_polarity == true || clear_polarity != enable_polarity)
332332
{
333-
RTLIL::Cell *inv = module->addCell(NEW_ID, ID($_NOT_));
333+
RTLIL::Cell *inv = module->addCell(NEWER_ID, ID($_NOT_));
334334
inv->setPort(ID::A, clear_sig);
335-
inv->setPort(ID::Y, module->addWire(NEW_ID));
335+
inv->setPort(ID::Y, module->addWire(NEWER_ID));
336336

337337
if (clear_polarity == true)
338338
clear_negative = inv->getPort(ID::Y);
339339
if (clear_polarity != enable_polarity)
340340
clear_enable = inv->getPort(ID::Y);
341341
}
342342

343-
RTLIL::Cell *data_gate = module->addCell(NEW_ID, ID($_AND_));
343+
RTLIL::Cell *data_gate = module->addCell(NEWER_ID, ID($_AND_));
344344
data_gate->setPort(ID::A, data_sig);
345345
data_gate->setPort(ID::B, clear_negative);
346-
data_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
346+
data_gate->setPort(ID::Y, data_sig = module->addWire(NEWER_ID));
347347

348-
RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? ID($_OR_) : ID($_AND_));
348+
RTLIL::Cell *enable_gate = module->addCell(NEWER_ID, enable_polarity ? ID($_OR_) : ID($_AND_));
349349
enable_gate->setPort(ID::A, enable_sig);
350350
enable_gate->setPort(ID::B, clear_enable);
351-
enable_gate->setPort(ID::Y, enable_sig = module->addWire(NEW_ID));
351+
enable_gate->setPort(ID::Y, enable_sig = module->addWire(NEWER_ID));
352352
}
353353

354354
if (preset_sig.size() == 1)
@@ -358,28 +358,28 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla
358358

359359
if (preset_polarity == false || preset_polarity != enable_polarity)
360360
{
361-
RTLIL::Cell *inv = module->addCell(NEW_ID, ID($_NOT_));
361+
RTLIL::Cell *inv = module->addCell(NEWER_ID, ID($_NOT_));
362362
inv->setPort(ID::A, preset_sig);
363-
inv->setPort(ID::Y, module->addWire(NEW_ID));
363+
inv->setPort(ID::Y, module->addWire(NEWER_ID));
364364

365365
if (preset_polarity == false)
366366
preset_positive = inv->getPort(ID::Y);
367367
if (preset_polarity != enable_polarity)
368368
preset_enable = inv->getPort(ID::Y);
369369
}
370370

371-
RTLIL::Cell *data_gate = module->addCell(NEW_ID, ID($_OR_));
371+
RTLIL::Cell *data_gate = module->addCell(NEWER_ID, ID($_OR_));
372372
data_gate->setPort(ID::A, data_sig);
373373
data_gate->setPort(ID::B, preset_positive);
374-
data_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
374+
data_gate->setPort(ID::Y, data_sig = module->addWire(NEWER_ID));
375375

376-
RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? ID($_OR_) : ID($_AND_));
376+
RTLIL::Cell *enable_gate = module->addCell(NEWER_ID, enable_polarity ? ID($_OR_) : ID($_AND_));
377377
enable_gate->setPort(ID::A, enable_sig);
378378
enable_gate->setPort(ID::B, preset_enable);
379-
enable_gate->setPort(ID::Y, enable_sig = module->addWire(NEW_ID));
379+
enable_gate->setPort(ID::Y, enable_sig = module->addWire(NEWER_ID));
380380
}
381381

382-
cell = module->addCell(NEW_ID, stringf("$_DLATCH_%c_", enable_polarity ? 'P' : 'N'));
382+
cell = module->addCell(NEWER_ID, stringf("$_DLATCH_%c_", enable_polarity ? 'P' : 'N'));
383383
cell->setPort(ID::D, data_sig);
384384
cell->setPort(ID::Q, iq_sig);
385385
cell->setPort(ID::E, enable_sig);
@@ -734,7 +734,7 @@ struct LibertyFrontend : public Frontend {
734734
if (wi->port_input) {
735735
for (auto wo : module->wires())
736736
if (wo->port_output) {
737-
RTLIL::Cell *spec = module->addCell(NEW_ID, ID($specify2));
737+
RTLIL::Cell *spec = module->addCell(NEWER_ID, ID($specify2));
738738
spec->setParam(ID::SRC_WIDTH, wi->width);
739739
spec->setParam(ID::DST_WIDTH, wo->width);
740740
spec->setParam(ID::T_FALL_MAX, 1000);

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