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correcting path of files #167

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7864cba
correcting path of files
Fnatu Jun 18, 2019
4199274
report of an unexpected cleaning of libxlnxdnn.so
Fnatu Jun 21, 2019
b297596
Add step in the Build from source section
Fnatu Jul 5, 2019
ca03f46
Esthetic arrangments
Fnatu Jul 9, 2019
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10 changes: 8 additions & 2 deletions README.md
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Expand Up @@ -280,10 +280,15 @@ Please follow the steps to build the design for zcu102 (ZU9 device based board)

1. Please generate a custom platform with 1x and 2x clocks using the steps described [here](./docs/CUSTOM_PLATFORM_GEN.md). With Chai-v2, we now have the DSPs operating at twice the frequency of the rest of the core.

1. Open `<path to CHaiDNN folder>/design/conv/scripts/mcps.tcl` file and modify the path of `xdc` file as shown below.
```
read_xdc <path to CHaiDNN folder>/design/conv/scripts/mcp_const.xdc
```
>**:pushpin: NOTE:**
> - Make sure the path to mcp_const.xdc is correct

1. Go to `CHaiDNN/design/build` folder.


1. Set SDx tool environment
- For BASH:
```sh
Expand Down Expand Up @@ -347,7 +352,8 @@ Follow the steps to compile the software stack.
```

1. Now run the following commands.

>**:pushpin: NOTE:**
> - running ultraclean erases the previous libxlnxdnn.so copied into <...>SD_Card/lib/ from <...>/design/build/sd_card
```sh
make ultraclean
make
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8 changes: 4 additions & 4 deletions docs/BUILD_USING_SDX_GUI.md
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Expand Up @@ -117,7 +117,7 @@ To build `CHaiDNN` using the Xilinx&reg; SDx Development Environment, perform th

19. In `SDS++ Linker` add the following in the `command`
```
sds++ -xp param:compiler.skipTimingCheckAndFrequencyScaling=1 -xp "vivado_prop:run.impl_1.{STEPS.OPT_DESIGN.ARGS.MORE OPTIONS}={-directive Explore}" -xp "vivado_prop:run.impl_1.{STEPS.PLACE_DESIGN.ARGS.MORE OPTIONS}={-directive Explore}" -xp "vivado_prop:run.impl_1.STEPS.PHYS_OPT_DESIGN.IS_ENABLED=1" -xp "vivado_prop:run.impl_1.{STEPS.PHYS_OPT_DESIGN.ARGS.MORE OPTIONS}={-directive Explore}" -xp "vivado_prop:run.impl_1.{STEPS.ROUTE_DESIGN.ARGS.MORE OPTIONS}={-directive Explore}" -xp "vivado_prop:run.synth_1.{STEPS.SYNTH_DESIGN.TCL.PRE}={<path to design>/src/conv/scripts/mcps.tcl}" -xp "vivado_prop:run.impl_1.{STEPS.PLACE_DESIGN.TCL.PRE}={<path to design>/src/conv/scripts/mcps.tcl}" -Wno-unused-label
sds++ -xp param:compiler.skipTimingCheckAndFrequencyScaling=1 -xp "vivado_prop:run.impl_1.{STEPS.OPT_DESIGN.ARGS.MORE OPTIONS}={-directive Explore}" -xp "vivado_prop:run.impl_1.{STEPS.PLACE_DESIGN.ARGS.MORE OPTIONS}={-directive Explore}" -xp "vivado_prop:run.impl_1.STEPS.PHYS_OPT_DESIGN.IS_ENABLED=1" -xp "vivado_prop:run.impl_1.{STEPS.PHYS_OPT_DESIGN.ARGS.MORE OPTIONS}={-directive Explore}" -xp "vivado_prop:run.impl_1.{STEPS.ROUTE_DESIGN.ARGS.MORE OPTIONS}={-directive Explore}" -xp "vivado_prop:run.synth_1.{STEPS.SYNTH_DESIGN.TCL.PRE}={<path to design>/conv/scripts/mcps.tcl}" -xp "vivado_prop:run.impl_1.{STEPS.PLACE_DESIGN.TCL.PRE}={<path to design>/conv/scripts/mcps.tcl}" -Wno-unused-label
```
20. In `SDS++ Linker`, Select `Libraries` and add the following libs
```
Expand All @@ -140,17 +140,17 @@ To build `CHaiDNN` using the Xilinx&reg; SDx Development Environment, perform th

24. Apply changes and close the window.

25. Open `<project name>/src/design/scripts/mcps.tcl` file and modify the path of `xdc` file as shown below.
25. Open `<project name>/src/design/conv/scripts/mcps.tcl` file and modify the path of `xdc` file as shown below.
```
read_xdc <path to project>/src/design/conv/scripts/mcp_const.xdc
```
>**:pushpin: NOTE:** `<path to project>` is the path to SDx project.

26. Select the Hardware functions.

- Navigate to `src/design/src/pool/src/pooling_layer_dp_2xio_top.cpp` file using SDx explorer, right click on `PoolTop` and select Toggle HW/SW.
- Navigate to `src/design/pool/src/pooling_layer_dp_2xio_top.cpp` file using SDx explorer, right click on `PoolTop` and select Toggle HW/SW.

- Navigate to `src/design/src/deconv/src/xi_deconv_top.cpp` file using SDx explorer, right click on `XiDeconvTop` and select Toggle HW/SW.
- Navigate to `src/design/deconv/src/xi_deconv_top.cpp` file using SDx explorer, right click on `XiDeconvTop` and select Toggle HW/SW.

>**:pushpin: NOTE:** When building `DietChai` don't map any function to HW. `XiConvolutionTop` will be mapped to HW by default.

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4 changes: 3 additions & 1 deletion docs/PERFORMANCE_EVAL.md
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Expand Up @@ -46,7 +46,9 @@


## Quick Performance Evaluation
CHai-v2 provides support for a variety of networks for classification, object detection and segmentation. Please refer to [Model Zoo](./MODELZOO.md) for list of networks and [Supported layers](./SUPPORTED_LAYERS.md) for list of layers that are required for these networks. While we believe that we have addressed most of the frequently-used heavy-lifting layers required in networks, we also understand that there might be some networks which might require support for some additional layers. We encourage users to add support for these layers and you could use the [software plugin](./SOFTWARE_LAYER_PLUGIN.md) methodology or the methodology described [here](./HW_SW_PARTITIONING.md) for efficient hardware software partitioning. But from a system design perspective, we understand that it might be useful to understand the performance of CHai on the layers that are already supported for a given network. We describe an API in this section which can be used to achieve this. For example, if a network is built with 50 layers and the support is missing for only two layers on CHai, then you could get a ball-park estimate on the latency of the 48 layers which are supported. Please note that these latency numbers are only an estimate and they could be optimistic or pessimistic based on the structure of the network. The reason for this is that the runtime of the accelerator fuses some layers for latency optimization.
<p>CHai-v2 provides support for a variety of networks for classification, object detection and segmentation. Please refer to [Model Zoo](./MODELZOO.md) for list of networks and [Supported layers](./SUPPORTED_LAYERS.md) for list of layers that are required for these networks. While we believe that we have addressed most of the frequently-used heavy-lifting layers required in networks, we also understand that there might be some networks which might require support for some additional layers.</p>
<p>We encourage users to add support for these layers and you could use the [software plugin](./SOFTWARE_LAYER_PLUGIN.md) methodology or the methodology described [here](./HW_SW_PARTITIONING.md) for efficient hardware software partitioning. But from a system design perspective, we understand that it might be useful to understand the performance of CHai on the layers that are already supported for a given network.</p>
<p>We describe an API in this section which can be used to achieve this. For example, if a network is built with 50 layers and the support is missing for only two layers on CHai, then you could get a ball-park estimate on the latency of the 48 layers which are supported. Please note that these latency numbers are only an estimate and they could be optimistic or pessimistic based on the structure of the network. The reason for this is that the runtime of the accelerator fuses some layers for latency optimization.</p>

<details>
<summary><big><strong>API</strong></big></summary>
Expand Down