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-44
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9 files changed

+1034
-44
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‎info.yaml‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,9 @@ project:
1919
source_files:
2020
- "defs.v"
2121
- "project.v"
22-
- "sky130_sram_1kbyte_1rw_32x256_8.v"
22+
- "scan_cell_2ph.v"
23+
- "scan_chain_2ph.v"
24+
- "sky130_sram_256B_1rw_32x64.v"
2325

2426
# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
2527
pinout:

‎src/config.json‎

Lines changed: 55 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -13,11 +13,12 @@
1313

1414
"//": "PL_TARGET_DENSITY_PCT - You can increase this if Global Placement fails with error GPL-0302.",
1515
"//": "Users have reported that values up to 80 worked well for them.",
16+
"FP_CORE_UTIL": 50,
1617
"PL_TARGET_DENSITY_PCT": 60,
1718

1819
"//": "CLOCK_PERIOD - Increase this in case you are getting setup time violations.",
1920
"//": "The value is in nanoseconds, so 20ns == 50MHz.",
20-
"CLOCK_PERIOD": 20,
21+
"CLOCK_PERIOD": 10000,
2122

2223
"//": "Hold slack margin - Increase them in case you are getting hold violations.",
2324
"PL_RESIZER_HOLD_SLACK_MARGIN": 0.1,
@@ -29,32 +30,60 @@
2930

3031
"//": "If you need a custom clock configuration, read the following documentation first:",
3132
"//": "https://tinytapeout.com/faq/#how-can-i-map-an-additional-external-clock-to-one-of-the-gpios",
32-
"CLOCK_PORT": "clk",
33-
34-
"sky130_sram_1kbyte_1rw_32x256_8": {
35-
"instances": {
36-
"mprj": {
37-
"location": [
38-
10,
39-
20
33+
"CLOCK_PORT": ["ui_in[3]", "ui_in[4]"],
34+
"CLOCK_NET": ["ui_in[3]", "ui_in[4]"],
35+
"FALLBACK_SDC_FILE": "src/project.sdc",
36+
"DESIGN_NAME" : "tt_um_openram_top",
37+
"EXTRA_LEFS" : ["src/sky130_sram_256B_1rw_32x64.lef"],
38+
"EXTRA_GDS" : ["src/sky130_sram_256B_1rw_32x64.gds"],
39+
40+
"MACROS": {
41+
"sky130_sram_256B_1rw_32x64": {
42+
"instances": {
43+
"SRAM": {
44+
"location": [
45+
2,
46+
10
47+
],
48+
"orientation": "S"
49+
}
50+
},
51+
"gds": [
52+
"dir::sky130_sram_256B_1rw_32x64.gds"
4053
],
41-
"orientation": "N"
42-
}
43-
},
44-
"gds": [
45-
"dir::./gds/sky130_sram_1kbyte_1rw_32x256_8.gds"
46-
],
47-
"lef": [
48-
"dir::./lef/sky130_sram_1kbyte_1rw_32x256_8.lef"
49-
],
50-
"nl": [
51-
"dir::./gl/sky130_sram_1kbyte_1rw_32x256_8.v"
52-
],
53-
"lib": {},
54-
"spice": [],
55-
"sdf": {}
56-
},
57-
54+
"lef": [
55+
"dir::sky130_sram_256B_1rw_32x64.lef"
56+
],
57+
"nl": [
58+
"dir::sky130_sram_256B_1rw_32x64.v"
59+
],
60+
"lib": {},
61+
"spice": [],
62+
"sdf": {}
63+
}
64+
},
65+
66+
"FP_PDN_CFG": "src/pdn_config.tcl",
67+
68+
"PDN_MACRO_CONNECTIONS": ["SRAM vccd1 vssd1 VPWR VGND"],
69+
"VERILOG_POWER_DEFINE": "USE_POWER_PINS",
70+
71+
"VDD_NETS": "VPWR",
72+
"GND_NETS": "VGND",
73+
74+
"FP_PDN_VPITCH": 240,
75+
"FP_PDN_VSPACING": 3,
76+
"FP_PDN_VOFFSET": 8,
77+
78+
"FP_PDN_VERTICAL_HALO": 5,
79+
"FP_PDN_HORIZONTAL_HALO": 5,
80+
"FP_TAP_HORIZONTAL_HALO": 5,
81+
"FP_TAP_VERTICAL_HALO": 5,
82+
"ERROR_ON_PDN_VIOLATIONS": false,
83+
84+
"FP_PDN_HORIZONTAL_LAYER": "m3",
85+
"FP_PDN_VERTICAL_LAYER": "m4",
86+
5887

5988
"//": "Configuration docs: https://openlane.readthedocs.io/en/latest/reference/configuration.html",
6089

@@ -83,8 +112,6 @@
83112
"FP_IO_HLENGTH": 2,
84113
"FP_IO_VLENGTH": 2,
85114

86-
"FP_PDN_VPITCH": 38.87,
87-
88115
"//": "Clock",
89116
"RUN_CTS": 1,
90117

‎src/pdn_config.tcl‎

Lines changed: 145 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,145 @@
1+
# Copyright 2020-2022 Efabless Corporation
2+
#
3+
# Licensed under the Apache License, Version 2.0 (the "License");
4+
# you may not use this file except in compliance with the License.
5+
# You may obtain a copy of the License at
6+
#
7+
# http://www.apache.org/licenses/LICENSE-2.0
8+
#
9+
# Unless required by applicable law or agreed to in writing, software
10+
# distributed under the License is distributed on an "AS IS" BASIS,
11+
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12+
# See the License for the specific language governing permissions and
13+
# limitations under the License.
14+
15+
source $::env(SCRIPTS_DIR)/openroad/common/set_global_connections.tcl
16+
set_global_connections
17+
18+
set secondary []
19+
foreach vdd $::env(VDD_NETS) gnd $::env(GND_NETS) {
20+
if { $vdd != $::env(VDD_NET)} {
21+
lappend secondary $vdd
22+
23+
set db_net [[ord::get_db_block] findNet $vdd]
24+
if {$db_net == "NULL"} {
25+
set net [odb::dbNet_create [ord::get_db_block] $vdd]
26+
$net setSpecial
27+
$net setSigType "POWER"
28+
}
29+
}
30+
31+
if { $gnd != $::env(GND_NET)} {
32+
lappend secondary $gnd
33+
34+
set db_net [[ord::get_db_block] findNet $gnd]
35+
if {$db_net == "NULL"} {
36+
set net [odb::dbNet_create [ord::get_db_block] $gnd]
37+
$net setSpecial
38+
$net setSigType "GROUND"
39+
}
40+
}
41+
}
42+
43+
set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET) \
44+
-secondary_power $secondary
45+
46+
if { $::env(FP_PDN_MULTILAYER) == 1 } {
47+
define_pdn_grid \
48+
-name stdcell_grid \
49+
-starts_with POWER \
50+
-voltage_domain CORE \
51+
-pins "$::env(FP_PDN_VERTICAL_LAYER) $::env(FP_PDN_HORIZONTAL_LAYER)"
52+
53+
add_pdn_stripe \
54+
-grid stdcell_grid \
55+
-layer $::env(FP_PDN_VERTICAL_LAYER) \
56+
-width $::env(FP_PDN_VWIDTH) \
57+
-pitch $::env(FP_PDN_VPITCH) \
58+
-offset $::env(FP_PDN_VOFFSET) \
59+
-spacing $::env(FP_PDN_VSPACING) \
60+
-starts_with POWER -extend_to_core_ring
61+
62+
add_pdn_stripe \
63+
-grid stdcell_grid \
64+
-layer $::env(FP_PDN_HORIZONTAL_LAYER) \
65+
-width $::env(FP_PDN_HWIDTH) \
66+
-pitch $::env(FP_PDN_HPITCH) \
67+
-offset $::env(FP_PDN_HOFFSET) \
68+
-spacing $::env(FP_PDN_HSPACING) \
69+
-starts_with POWER -extend_to_core_ring
70+
71+
add_pdn_connect \
72+
-grid stdcell_grid \
73+
-layers "$::env(FP_PDN_VERTICAL_LAYER) $::env(FP_PDN_HORIZONTAL_LAYER)"
74+
} else {
75+
define_pdn_grid \
76+
-name stdcell_grid \
77+
-starts_with POWER \
78+
-voltage_domain CORE \
79+
-pins $::env(FP_PDN_VERTICAL_LAYER)
80+
81+
add_pdn_stripe \
82+
-grid stdcell_grid \
83+
-layer $::env(FP_PDN_VERTICAL_LAYER) \
84+
-width $::env(FP_PDN_VWIDTH) \
85+
-pitch $::env(FP_PDN_VPITCH) \
86+
-offset $::env(FP_PDN_VOFFSET) \
87+
-spacing $::env(FP_PDN_VSPACING) \
88+
-starts_with POWER -extend_to_core_ring
89+
}
90+
91+
# Adds the standard cell rails if enabled.
92+
if { $::env(FP_PDN_ENABLE_RAILS) == 1 } {
93+
add_pdn_stripe \
94+
-grid stdcell_grid \
95+
-layer $::env(FP_PDN_RAIL_LAYER) \
96+
-width $::env(FP_PDN_RAIL_WIDTH) \
97+
-followpins \
98+
-starts_with POWER
99+
100+
add_pdn_connect \
101+
-grid stdcell_grid \
102+
-layers "$::env(FP_PDN_RAIL_LAYER) $::env(FP_PDN_VERTICAL_LAYER)"
103+
}
104+
105+
106+
# Adds the core ring if enabled.
107+
if { $::env(FP_PDN_CORE_RING) == 1 } {
108+
if { $::env(FP_PDN_MULTILAYER) == 1 } {
109+
add_pdn_ring \
110+
-grid stdcell_grid \
111+
-layers "$::env(FP_PDN_VERTICAL_LAYER) $::env(FP_PDN_HORIZONTAL_LAYER)" \
112+
-widths "$::env(FP_PDN_CORE_RING_VWIDTH) $::env(FP_PDN_CORE_RING_HWIDTH)" \
113+
-spacings "$::env(FP_PDN_CORE_RING_VSPACING) $::env(FP_PDN_CORE_RING_HSPACING)" \
114+
-core_offset "$::env(FP_PDN_CORE_RING_VOFFSET) $::env(FP_PDN_CORE_RING_HOFFSET)"
115+
} else {
116+
throw APPLICATION "FP_PDN_CORE_RING cannot be used when FP_PDN_MULTILAYER is set to false."
117+
# add_pdn_ring \
118+
# -grid stdcell_grid \
119+
# -layers "$::env(FP_PDN_VERTICAL_LAYER)" \
120+
# -widths "$::env(FP_PDN_CORE_RING_VWIDTH)" \
121+
# -spacings "$::env(FP_PDN_CORE_RING_VSPACING)" \
122+
# -core_offset "$::env(FP_PDN_CORE_RING_VOFFSET)"
123+
}
124+
}
125+
126+
# define_pdn_grid \
127+
# -macro \
128+
# -default \
129+
# -name macro \
130+
# -starts_with POWER \
131+
# -halo "$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)"
132+
133+
134+
# # add_pdn_stripe \
135+
# # -grid macro \
136+
# # -layer $::env(FP_PDN_VERTICAL_LAYER) \
137+
# # -width $::env(FP_PDN_VWIDTH) \
138+
# # -pitch $::env(FP_PDN_VPITCH) \
139+
# # -offset $::env(FP_PDN_VOFFSET) \
140+
# # -spacing $::env(FP_PDN_VSPACING) \
141+
# # -starts_with POWER -extend_to_core_ring
142+
143+
# add_pdn_connect \
144+
# -grid macro \
145+
# -layers "met3 met4"

‎src/project.sdc‎

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,36 @@
1+
# Shared constants, copied from base.sdc
2+
set input_delay_value [ expr $::env(CLOCK_PERIOD) * $::env(IO_PCT) ]
3+
set output_delay_value [ expr $::env(CLOCK_PERIOD) * $::env(IO_PCT) ]
4+
set_max_fanout $::env(MAX_FANOUT_CONSTRAINT) [ current_design ]
5+
set cap_load [ expr $::env(OUTPUT_CAP_LOAD) / 1000.0 ] ;# fF -> pF
6+
7+
# Remove clock net from inputs
8+
set idx [ lsearch [ all_inputs ] "clk" ]
9+
set all_inputs_wo_clk [ lreplace [ all_inputs ] $idx $idx ]
10+
set idx [ lsearch $all_inputs_wo_clk "ui_in\[3\]" ]
11+
set all_inputs_wo_clk [ lreplace $all_inputs_wo_clk $idx $idx ]
12+
set idx [ lsearch $all_inputs_wo_clk "ui_in\[4\]" ]
13+
set all_inputs_wo_clk [ lreplace $all_inputs_wo_clk $idx $idx ]
14+
15+
# configure sclka
16+
create_clock [ get_ports "ui_in\[3\]" ] -name sclka -period $::env(CLOCK_PERIOD)
17+
set_input_delay $input_delay_value -clock [ get_clocks sclka ] $all_inputs_wo_clk
18+
set_output_delay $output_delay_value -clock [ get_clocks sclka ] [ all_outputs ]
19+
set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINTY) [ get_clocks sclka ]
20+
set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [ get_clocks sclka ]
21+
22+
# configure sclkb
23+
create_clock [ get_ports "ui_in\[4\]" ] -name sclkb -period $::env(CLOCK_PERIOD)
24+
set_input_delay $input_delay_value -clock [ get_clocks sclkb ] $all_inputs_wo_clk
25+
set_output_delay $output_delay_value -clock [ get_clocks sclkb ] [ all_outputs ]
26+
set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINTY) [ get_clocks sclkb ]
27+
set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [ get_clocks sclkb ]
28+
29+
# rp2040_clk and fpga_clk are mesochronous, and they never interact
30+
set_clock_groups -asynchronous -group {sclka} -group { sclkb}
31+
32+
# Miscellanea
33+
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) $all_inputs_wo_clk
34+
set_load $cap_load [ all_outputs ]
35+
set_timing_derate -early [ expr {1-$::env(SYNTH_TIMING_DERATE)} ]
36+
set_timing_derate -late [ expr {1+$::env(SYNTH_TIMING_DERATE)} ]

‎src/project.v‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -5,14 +5,14 @@
55

66
`default_nettype none
77
//`timescale 1ns / 1ps
8-
`include "sky130_sram_1kbyte_1rw_32x256_8.v"
8+
`include "sky130_sram_256B_1rw_32x64.v"
99
`include "scan_chain_2ph.v"
1010
`include "defs.v"
1111
module tt_um_openram_top (
12-
`ifdef USE_POWER_PINS
13-
input VPWR,
14-
input VGND,
15-
`endif
12+
`ifdef USE_POWER_PINS
13+
input VPWR,
14+
input VGND,
15+
`endif
1616
input wire [7:0] ui_in, // Dedicated inputs
1717
output wire [7:0] uo_out, // Dedicated outputs
1818
input wire [7:0] uio_in, // IOs: Input path
@@ -24,7 +24,7 @@ module tt_um_openram_top (
2424

2525
);
2626

27-
parameter ADDR_WIDTH = 9;
27+
parameter ADDR_WIDTH = 6;
2828
parameter DATA_WIDTH = 33;
2929
parameter WMASK_WIDTH = 4;
3030
parameter SCAN_WIDTH = ADDR_WIDTH + DATA_WIDTH + DATA_WIDTH;
@@ -41,7 +41,7 @@ wire [WMASK_WIDTH-1:0] wmask;
4141
wire [SCAN_WIDTH-1:0] scan_data_out;
4242
wire scan_out;
4343

44-
wire scan_in, scan_enable, phase_enable, scan_mode, csb, web, sclka, sclkb, spare_wen;
44+
wire scan_in, scan_enable, scan_mode, csb, web, sclka, sclkb, spare_wen;
4545
assign spare_wen = ui_in[7];
4646
assign web = ui_in[6];
4747
assign csb = ui_in[5];
@@ -57,12 +57,12 @@ assign uo_out[1] = scan_data_out[0];
5757
assign uo_out[0] = scan_out;
5858

5959

60-
sky130_sram_1kbyte_1rw_32x256_8 SRAM
60+
sky130_sram_256B_1rw_32x64 SRAM
6161
(
62-
`ifdef USE_POWER_PINS
63-
.vccd1(VPWR),
64-
.vssd1(VGND),
65-
`endif
62+
`ifdef USE_POWER_PINS
63+
.vccd1(VPWR),
64+
.vssd1(VGND),
65+
`endif
6666
.clk0 (sclka), //SRAM USES A CLK
6767
.csb0 (csb),
6868
.web0 (web),

‎src/sky130_sram_1kbyte_1rw_32x256_8.v‎

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,8 @@
22
// Words: 256
33
// Word size: 32
44
// Write size: 8
5-
5+
`ifndef SRAM_GUARD
6+
`define SRAM_GUARD
67

78
module sky130_sram_1kbyte_1rw_32x256_8(
89
`ifdef USE_POWER_PINS
@@ -53,15 +54,15 @@ module sky130_sram_1kbyte_1rw_32x256_8(
5354
addr0_reg = addr0;
5455
din0_reg = din0;
5556

56-
`ifdef SIMULATION
57+
/* `ifdef SIMULATION
5758
#(T_HOLD) dout0 <= 33'bx;
5859
if ( !csb0_reg && web0_reg && VERBOSE )
5960
$display($time," Reading %m addr0=%b dout0=%b",addr0_reg,mem[addr0_reg]);
6061
if ( !csb0_reg && !web0_reg && VERBOSE )
6162
$display($time," Writing %m addr0=%b din0=%b wmask0=%b",addr0_reg,din0_reg,wmask0_reg);
6263
`else
6364
dout0 <= 33'bx;
64-
`endif
65+
`endif */
6566
end
6667

6768
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
@@ -98,3 +99,5 @@ reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
9899
end
99100

100101
endmodule
102+
103+
`endif

‎src/sky130_sram_256B_1rw_32x64.gds‎

2.82 MB
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