feat: update project tt_um_rc_servo_motor_xy_ea from yavarhadi/tt09-wokiwi-yavar

Commit: 15aaa657163a0b6423539b7ec520c504de215b2d
Workflow: https://github.com/yavarhadi/tt09-wokiwi-yavar/actions/runs/19012096585

Author: TinyTapeoutBot

projects/tt_um_rc_servo_motor_xy_ea/commit_id.json

@@ -1,8 +1,8 @@
 {
   "app": "Tiny Tapeout main f77b61f7",
   "repo": "https://github.com/yavarhadi/rc_servo_motor_xy",
-  "commit": "0a4b6577c6a3b4089e9bde242d8e9ab1d66b371c",
-  "workflow_url": "https://github.com/yavarhadi/rc_servo_motor_xy/actions/runs/18971376852",
+  "commit": "15aaa657163a0b6423539b7ec520c504de215b2d",
+  "workflow_url": "https://github.com/yavarhadi/rc_servo_motor_xy/actions/runs/19012096585",
   "project_id": 3066,
   "sort_id": 1761911704566
 }

projects/tt_um_rc_servo_motor_xy_ea/info.yaml

@@ -36,10 +36,10 @@ pinout:
   ui[7]: ""
 
   # Outputs
-  uo[0]: "pwm_pin_x_o"
-  uo[1]: "pwm_pin_y_o"
-  uo[2]: ""
-  uo[3]: ""
+  uo[0]: "pwm_pin_x_o"   #output to rc motor
+  uo[1]: "pwm_pin_y_o"   # output to rc motor
+  uo[2]: "pwm_x_o"       #output to comp
+  uo[3]: "pwm_y_o"      #output to comp
   uo[4]: ""
   uo[5]: ""
   uo[6]: ""

projects/tt_um_rc_servo_motor_xy_ea/stats/metrics.csv

@@ -1,23 +1,23 @@
 Metric,Value
 design__lint_error__count,0
 design__lint_timing_construct__count,0
-design__lint_warning__count,4
+design__lint_warning__count,2
 design__inferred_latch__count,0
-design__instance__count,2825
-design__instance__area,21435.6
+design__instance__count,2225
+design__instance__area,16958.8
 design__instance_unmapped__count,0
 synthesis__check_error__count,0
 design__max_slew_violation__count__corner:nom_tt_025C_1v80,0
 design__max_fanout_violation__count__corner:nom_tt_025C_1v80,0
 design__max_cap_violation__count__corner:nom_tt_025C_1v80,0
-power__internal__total,0.00004627263842849061
-power__switching__total,0.00004257020918885246
-power__leakage__total,2.048979830249209E-8
-power__total,0.00008886333671398461
+power__internal__total,0.0000331419832946267
+power__switching__total,0.000024426619347650558
+power__leakage__total,1.6736551700091695E-8
+power__total,0.000057585340982768685
 clock__skew__worst_hold__corner:nom_tt_025C_1v80,0.0
 clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.0
-timing__hold__ws__corner:nom_tt_025C_1v80,8.302794242694095
-timing__setup__ws__corner:nom_tt_025C_1v80,10.760145079508069
+timing__hold__ws__corner:nom_tt_025C_1v80,8.291376708785938
+timing__setup__ws__corner:nom_tt_025C_1v80,10.792554710959534
 timing__hold__tns__corner:nom_tt_025C_1v80,0.0
 timing__setup__tns__corner:nom_tt_025C_1v80,0.0
 timing__hold__wns__corner:nom_tt_025C_1v80,0
@@ -33,8 +33,8 @@ design__max_fanout_violation__count__corner:nom_ss_100C_1v60,0
 design__max_cap_violation__count__corner:nom_ss_100C_1v60,0
 clock__skew__worst_hold__corner:nom_ss_100C_1v60,0.0
 clock__skew__worst_setup__corner:nom_ss_100C_1v60,0.0
-timing__hold__ws__corner:nom_ss_100C_1v60,8.649573746510985
-timing__setup__ws__corner:nom_ss_100C_1v60,9.597773514274527
+timing__hold__ws__corner:nom_ss_100C_1v60,8.651412275891762
+timing__setup__ws__corner:nom_ss_100C_1v60,9.585629450398509
 timing__hold__tns__corner:nom_ss_100C_1v60,0.0
 timing__setup__tns__corner:nom_ss_100C_1v60,0.0
 timing__hold__wns__corner:nom_ss_100C_1v60,0
@@ -50,8 +50,8 @@ design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,0
 design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0
 clock__skew__worst_hold__corner:nom_ff_n40C_1v95,0.0
 clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.0
-timing__hold__ws__corner:nom_ff_n40C_1v95,8.165433005310529
-timing__setup__ws__corner:nom_ff_n40C_1v95,11.238433612935609
+timing__hold__ws__corner:nom_ff_n40C_1v95,8.152640571169794
+timing__setup__ws__corner:nom_ff_n40C_1v95,11.262443740834415
 timing__hold__tns__corner:nom_ff_n40C_1v95,0.0
 timing__setup__tns__corner:nom_ff_n40C_1v95,0.0
 timing__hold__wns__corner:nom_ff_n40C_1v95,0
@@ -67,8 +67,8 @@ design__max_fanout_violation__count,0
 design__max_cap_violation__count,0
 clock__skew__worst_hold,0.0
 clock__skew__worst_setup,0.0
-timing__hold__ws,8.157396766741803
-timing__setup__ws,9.580065012441715
+timing__hold__ws,8.146256344508432
+timing__setup__ws,9.549128869030206
 timing__hold__tns,0.0
 timing__setup__tns,0.0
 timing__hold__wns,0
@@ -84,18 +84,18 @@ design__core__bbox,2.76 2.72 158.24 223.04
 design__io,45
 design__die__area,36347.4
 design__core__area,34255.4
-design__instance__count__stdcell,2825
-design__instance__area__stdcell,21435.6
+design__instance__count__stdcell,2225
+design__instance__area__stdcell,16958.8
 design__instance__count__macros,0
 design__instance__area__macros,0
-design__instance__utilization,0.625758
-design__instance__utilization__stdcell,0.625758
-design__instance__count__class:inverter,331
-design__instance__count__class:sequential_cell,274
-design__instance__count__class:multi_input_combinational_cell,1635
+design__instance__utilization,0.495069
+design__instance__utilization__stdcell,0.495069
+design__instance__count__class:inverter,87
+design__instance__count__class:sequential_cell,226
+design__instance__count__class:multi_input_combinational_cell,1346
 flow__warnings__count,1
 flow__errors__count,0
-design__instance__count__class:fill_cell,2179
+design__instance__count__class:fill_cell,2470
 design__instance__count__class:tap_cell,456
 design__power_grid_violation__count__net:VPWR,0
 design__power_grid_violation__count__net:VGND,0
@@ -105,51 +105,46 @@ timing__drv__floating__pins,0
 design__instance__displacement__total,0
 design__instance__displacement__mean,0
 design__instance__displacement__max,0
-route__wirelength__estimated,35406.7
+route__wirelength__estimated,31837.8
 design__violations,0
-design__instance__count__class:timing_repair_buffer,128
+design__instance__count__class:timing_repair_buffer,110
 design__instance__count__setup_buffer,0
 design__instance__count__hold_buffer,0
 antenna__violating__nets,0
 antenna__violating__pins,0
 route__antenna_violation__count,0
-antenna_diodes_count,1
-design__instance__count__class:antenna_cell,1
-route__net,2387
+antenna_diodes_count,0
+route__net,1788
 route__net__special,2
-route__drc_errors__iter:1,561
-route__wirelength__iter:1,39770
-route__drc_errors__iter:2,219
-route__wirelength__iter:2,39368
-route__drc_errors__iter:3,145
-route__wirelength__iter:3,39212
-route__drc_errors__iter:4,3
-route__wirelength__iter:4,39228
-route__drc_errors__iter:5,3
-route__wirelength__iter:5,39228
-route__drc_errors__iter:6,0
-route__wirelength__iter:6,39212
+route__drc_errors__iter:1,402
+route__wirelength__iter:1,35823
+route__drc_errors__iter:2,132
+route__wirelength__iter:2,35532
+route__drc_errors__iter:3,110
+route__wirelength__iter:3,35567
+route__drc_errors__iter:4,0
+route__wirelength__iter:4,35546
 route__drc_errors,0
-route__wirelength,39212
-route__vias,15123
-route__vias__singlecut,15123
+route__wirelength,35546
+route__vias,11949
+route__vias__singlecut,11949
 route__vias__multicut,0
 design__disconnected_pin__count,14
 design__critical_disconnected_pin__count,0
-route__wirelength__max,285.92
-timing__unannotated_net__count__corner:nom_tt_025C_1v80,36
+route__wirelength__max,288.63
+timing__unannotated_net__count__corner:nom_tt_025C_1v80,34
 timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,0
-timing__unannotated_net__count__corner:nom_ss_100C_1v60,36
+timing__unannotated_net__count__corner:nom_ss_100C_1v60,34
 timing__unannotated_net_filtered__count__corner:nom_ss_100C_1v60,0
-timing__unannotated_net__count__corner:nom_ff_n40C_1v95,36
+timing__unannotated_net__count__corner:nom_ff_n40C_1v95,34
 timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95,0
 design__max_slew_violation__count__corner:min_tt_025C_1v80,0
 design__max_fanout_violation__count__corner:min_tt_025C_1v80,0
 design__max_cap_violation__count__corner:min_tt_025C_1v80,0
 clock__skew__worst_hold__corner:min_tt_025C_1v80,0.0
 clock__skew__worst_setup__corner:min_tt_025C_1v80,0.0
-timing__hold__ws__corner:min_tt_025C_1v80,8.290913079637743
-timing__setup__ws__corner:min_tt_025C_1v80,10.780601605449153
+timing__hold__ws__corner:min_tt_025C_1v80,8.282531339653982
+timing__setup__ws__corner:min_tt_025C_1v80,10.80974984565124
 timing__hold__tns__corner:min_tt_025C_1v80,0.0
 timing__setup__tns__corner:min_tt_025C_1v80,0.0
 timing__hold__wns__corner:min_tt_025C_1v80,0
@@ -160,15 +155,15 @@ timing__hold_r2r_vio__count__corner:min_tt_025C_1v80,0
 timing__setup_vio__count__corner:min_tt_025C_1v80,0
 timing__setup_r2r__ws__corner:min_tt_025C_1v80,Infinity
 timing__setup_r2r_vio__count__corner:min_tt_025C_1v80,0
-timing__unannotated_net__count__corner:min_tt_025C_1v80,36
+timing__unannotated_net__count__corner:min_tt_025C_1v80,34
 timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80,0
 design__max_slew_violation__count__corner:min_ss_100C_1v60,0
 design__max_fanout_violation__count__corner:min_ss_100C_1v60,0
 design__max_cap_violation__count__corner:min_ss_100C_1v60,0
 clock__skew__worst_hold__corner:min_ss_100C_1v60,0.0
 clock__skew__worst_setup__corner:min_ss_100C_1v60,0.0
-timing__hold__ws__corner:min_ss_100C_1v60,8.62675999497735
-timing__setup__ws__corner:min_ss_100C_1v60,9.631632652947937
+timing__hold__ws__corner:min_ss_100C_1v60,8.635405523959225
+timing__setup__ws__corner:min_ss_100C_1v60,9.615450041683324
 timing__hold__tns__corner:min_ss_100C_1v60,0.0
 timing__setup__tns__corner:min_ss_100C_1v60,0.0
 timing__hold__wns__corner:min_ss_100C_1v60,0
@@ -179,15 +174,15 @@ timing__hold_r2r_vio__count__corner:min_ss_100C_1v60,0
 timing__setup_vio__count__corner:min_ss_100C_1v60,0
 timing__setup_r2r__ws__corner:min_ss_100C_1v60,Infinity
 timing__setup_r2r_vio__count__corner:min_ss_100C_1v60,0
-timing__unannotated_net__count__corner:min_ss_100C_1v60,36
+timing__unannotated_net__count__corner:min_ss_100C_1v60,34
 timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60,0
 design__max_slew_violation__count__corner:min_ff_n40C_1v95,0
 design__max_fanout_violation__count__corner:min_ff_n40C_1v95,0
 design__max_cap_violation__count__corner:min_ff_n40C_1v95,0
 clock__skew__worst_hold__corner:min_ff_n40C_1v95,0.0
 clock__skew__worst_setup__corner:min_ff_n40C_1v95,0.0
-timing__hold__ws__corner:min_ff_n40C_1v95,8.157396766741803
-timing__setup__ws__corner:min_ff_n40C_1v95,11.251503158751127
+timing__hold__ws__corner:min_ff_n40C_1v95,8.146256344508432
+timing__setup__ws__corner:min_ff_n40C_1v95,11.27354597139466
 timing__hold__tns__corner:min_ff_n40C_1v95,0.0
 timing__setup__tns__corner:min_ff_n40C_1v95,0.0
 timing__hold__wns__corner:min_ff_n40C_1v95,0
@@ -198,15 +193,15 @@ timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95,0
 timing__setup_vio__count__corner:min_ff_n40C_1v95,0
 timing__setup_r2r__ws__corner:min_ff_n40C_1v95,Infinity
 timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95,0
-timing__unannotated_net__count__corner:min_ff_n40C_1v95,36
+timing__unannotated_net__count__corner:min_ff_n40C_1v95,34
 timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95,0
 design__max_slew_violation__count__corner:max_tt_025C_1v80,0
 design__max_fanout_violation__count__corner:max_tt_025C_1v80,0
 design__max_cap_violation__count__corner:max_tt_025C_1v80,0
 clock__skew__worst_hold__corner:max_tt_025C_1v80,0.0
 clock__skew__worst_setup__corner:max_tt_025C_1v80,0.0
-timing__hold__ws__corner:max_tt_025C_1v80,8.30719250235284
-timing__setup__ws__corner:max_tt_025C_1v80,10.749770267094132
+timing__hold__ws__corner:max_tt_025C_1v80,8.301096933686043
+timing__setup__ws__corner:max_tt_025C_1v80,10.773640062798657
 timing__hold__tns__corner:max_tt_025C_1v80,0.0
 timing__setup__tns__corner:max_tt_025C_1v80,0.0
 timing__hold__wns__corner:max_tt_025C_1v80,0
@@ -217,15 +212,15 @@ timing__hold_r2r_vio__count__corner:max_tt_025C_1v80,0
 timing__setup_vio__count__corner:max_tt_025C_1v80,0
 timing__setup_r2r__ws__corner:max_tt_025C_1v80,Infinity
 timing__setup_r2r_vio__count__corner:max_tt_025C_1v80,0
-timing__unannotated_net__count__corner:max_tt_025C_1v80,36
+timing__unannotated_net__count__corner:max_tt_025C_1v80,34
 timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80,0
 design__max_slew_violation__count__corner:max_ss_100C_1v60,0
 design__max_fanout_violation__count__corner:max_ss_100C_1v60,0
 design__max_cap_violation__count__corner:max_ss_100C_1v60,0
 clock__skew__worst_hold__corner:max_ss_100C_1v60,0.0
 clock__skew__worst_setup__corner:max_ss_100C_1v60,0.0
-timing__hold__ws__corner:max_ss_100C_1v60,8.657488304632771
-timing__setup__ws__corner:max_ss_100C_1v60,9.580065012441715
+timing__hold__ws__corner:max_ss_100C_1v60,8.669914809254243
+timing__setup__ws__corner:max_ss_100C_1v60,9.549128869030206
 timing__hold__tns__corner:max_ss_100C_1v60,0.0
 timing__setup__tns__corner:max_ss_100C_1v60,0.0
 timing__hold__wns__corner:max_ss_100C_1v60,0
@@ -236,15 +231,15 @@ timing__hold_r2r_vio__count__corner:max_ss_100C_1v60,0
 timing__setup_vio__count__corner:max_ss_100C_1v60,0
 timing__setup_r2r__ws__corner:max_ss_100C_1v60,Infinity
 timing__setup_r2r_vio__count__corner:max_ss_100C_1v60,0
-timing__unannotated_net__count__corner:max_ss_100C_1v60,36
+timing__unannotated_net__count__corner:max_ss_100C_1v60,34
 timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60,0
 design__max_slew_violation__count__corner:max_ff_n40C_1v95,0
 design__max_fanout_violation__count__corner:max_ff_n40C_1v95,0
 design__max_cap_violation__count__corner:max_ff_n40C_1v95,0
 clock__skew__worst_hold__corner:max_ff_n40C_1v95,0.0
 clock__skew__worst_setup__corner:max_ff_n40C_1v95,0.0
-timing__hold__ws__corner:max_ff_n40C_1v95,8.168614460499873
-timing__setup__ws__corner:max_ff_n40C_1v95,11.231520920099578
+timing__hold__ws__corner:max_ff_n40C_1v95,8.159604778355623
+timing__setup__ws__corner:max_ff_n40C_1v95,11.250156680228782
 timing__hold__tns__corner:max_ff_n40C_1v95,0.0
 timing__setup__tns__corner:max_ff_n40C_1v95,0.0
 timing__hold__wns__corner:max_ff_n40C_1v95,0
@@ -255,25 +250,25 @@ timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0
 timing__setup_vio__count__corner:max_ff_n40C_1v95,0
 timing__setup_r2r__ws__corner:max_ff_n40C_1v95,Infinity
 timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95,0
-timing__unannotated_net__count__corner:max_ff_n40C_1v95,36
+timing__unannotated_net__count__corner:max_ff_n40C_1v95,34
 timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95,0
-timing__unannotated_net__count,36
+timing__unannotated_net__count,34
 timing__unannotated_net_filtered__count,0
 design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79999
 design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.8
-design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.00000971577
-design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.00000905427
-design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,7.2855E-7
-design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.00000905427
-design_powergrid__voltage__worst,0.00000905427
+design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.00000870962
+design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.00000775721
+design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,4.78624E-7
+design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.00000775721
+design_powergrid__voltage__worst,0.00000775721
 design_powergrid__voltage__worst__net:VPWR,1.79999
-design_powergrid__drop__worst,0.00000971577
-design_powergrid__drop__worst__net:VPWR,0.00000971577
-design_powergrid__voltage__worst__net:VGND,0.00000905427
-design_powergrid__drop__worst__net:VGND,0.00000905427
+design_powergrid__drop__worst,0.00000870962
+design_powergrid__drop__worst__net:VPWR,0.00000870962
+design_powergrid__voltage__worst__net:VGND,0.00000775721
+design_powergrid__drop__worst__net:VGND,0.00000775721
 ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
-ir__drop__avg,7.339999999999999816081906571507698089362747850827872753143310546875E-7
-ir__drop__worst,0.000009720000000000000110723062662909654818577109836041927337646484375
+ir__drop__avg,4.829999999999999707317997234279349783037105225957930088043212890625E-7
+ir__drop__worst,0.00000870999999999999961644396584414806739005143754184246063232421875
 magic__drc_error__count,0
 magic__illegal_overlap__count,0
 design__lvs_device_difference__count,0