feat: update project tt_um_toivoh_basilisc_2816_cpu_OL2 from toivoh/t…

…t07-basilisc-2816-cpu-OL2

Commit: 621db63cea649f7603f18e2b491a3fb1ec2c49d0
Workflow: https://github.com/toivoh/tt07-basilisc-2816-cpu-OL2/actions/runs/9281394768

projects/tt_um_toivoh_basilisc_2816_cpu_OL2/commit_id.json

@@ -1,8 +1,8 @@
 {
-  "app": "Tiny Tapeout tt07 98e94823",
+  "app": "Tiny Tapeout tt07 f56fdf7c",
   "repo": "https://github.com/toivoh/tt07-basilisc-2816-cpu-OL2",
-  "commit": "08ccea7dc7143d967f2719b852ce2dbb80138e1e",
-  "workflow_url": "https://github.com/toivoh/tt07-basilisc-2816-cpu-OL2/actions/runs/9267507288",
+  "commit": "621db63cea649f7603f18e2b491a3fb1ec2c49d0",
+  "workflow_url": "https://github.com/toivoh/tt07-basilisc-2816-cpu-OL2/actions/runs/9281394768",
   "sort_id": 1716877530865,
   "openlane_version": "OpenLane2 2.0.7",
   "pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"

projects/tt_um_toivoh_basilisc_2816_cpu_OL2/docs/info.md

@@ -7,6 +7,34 @@ You can also include images in this folder and reference them in the markdown. E
 512 kb in size, and the combined size of all images must be less than 1 MB.
 -->
 
-## What it is
+## Overview
 
-This is an OpenLane 2 version of `tt_um_toivoh_basilisc_2816` / https://github.com/toivoh/tt07-basilisc-2816-cpu. It omits the `mul` instruction but increases the length of the prefetch queue to 3 words. For more details, see the documentation of that project / https://github.com/toivoh/tt07-basilisc-2816-cpu/blob/main/docs/info.md.
+Basilisc-2816 v0.1 is a small 2-bit serial 2/8/16 bit processor that fits into one Tiny Tapeout tile.
+The CPU has been designed around the constraints of
+
+- small area,
+- 4 pin serial memory interface to a RAM emulator implemented in a RP2040 microcontroller, which can be supported by the RP2040 microcontroller on the Tiny Tapeout 06 Demo Board.
+
+and a later version is intended to be included in the next version of the AnemoneGrafx-8 retro console https://github.com/toivoh/tt06-retro-console (motivating the constraints).
+
+Features:
+
+- 2-bit serial execution:
+	- ALU operations etc are calculated 2 bits/cycle
+	- 2-bit-serial register file with two read/write ports realized as a bank of shift registers
+	- Saves area compared to processing 8/16 bits per cycle
+	- No point in calculating faster than the memory interface allows
+- 8x 8-bit registers that can be paired into 4x 16-bit registers
+- 16 bits/instruction (some instructions might take an additional 16 bit immediate)
+- 64 kB address space
+- Quite regular and orthogonal instruction encoding
+- Many addressing modes
+- Variable shift instructions
+- 8x8 and 8x16 bit multiply instructions, producing 2 result bits per cycle like everything else
+- 13 branch conditions + relative call
+- Instruction prefetch queue
+
+This is the v0.1b version, which is hardened using OpenLane 2, omits the `mul` instruction, but has a prefetch queue of 3 instruction words.
+The v0.1a version `tt_um_toivoh_basilisc_2816` can be found at https://github.com/toivoh/tt07-basilisc-2816-cpu.
+
+For more details, see https://github.com/toivoh/tt07-basilisc-2816-cpu/blob/main/docs/info.md or the documentation of `tt_um_toivoh_basilisc_2816`.