feat: update project tt_um_chip_rom from TinyTapeout/tt-chip-rom

Commit: 7b1d3638536711cabd8fd4d131e10a37cdd208df Workflow: https://github.com/TinyTapeout/tt-chip-rom/actions/runs/9287983026
TinyTapeout · May 29, 2024 · 94b9083 · 94b9083
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commit 94b9083
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diff --git a/projects/tt_um_chip_rom/commit_id.json b/projects/tt_um_chip_rom/commit_id.json
@@ -1,8 +1,8 @@
 {
   "app": "Tiny Tapeout tt07 11b2d371",
   "repo": "https://github.com/TinyTapeout/tt-chip-rom",
-  "commit": "6abaf11f9f2bcf9356140b4521f4c82d4efd0b20",
-  "workflow_url": "https://github.com/TinyTapeout/tt-chip-rom/actions/runs/9287585076",
+  "commit": "7b1d3638536711cabd8fd4d131e10a37cdd208df",
+  "workflow_url": "https://github.com/TinyTapeout/tt-chip-rom/actions/runs/9287983026",
   "sort_id": 1713709041187,
   "openlane_version": "OpenLane 337ffbf4749b8bc6e8d8742ed9a595934142198b",
   "pdk_version": "open_pdks cd1748bb197f9b7af62a54507de6624e30363943"

diff --git a/projects/tt_um_chip_rom/docs/info.md b/projects/tt_um_chip_rom/docs/info.md
@@ -11,7 +11,7 @@ The ROM layout is as follows:
 | 0       | 8      | 7-segment | Shuttle name (e.g. "tt07"), null-padded  |
 | 8       | 8      | 7-segment | Git commit hash                          |
 | 32      | 96     | ASCII     | Chip descriptor (see below)              |
-| 248     | 4      | binary    | Magic value: "TT\\xFA\\xBB"              |
+| 248     | 4      | binary    | Magic value: `"TT\xFA\xBB"`              |
 | 252     | 4      | binary    | CRC32 of the ROM contents, little-endian |
 
 ### The chip descriptor

diff --git a/projects/tt_um_chip_rom/stats/metrics.csv b/projects/tt_um_chip_rom/stats/metrics.csv
@@ -1,2 +1,2 @@
 design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY
-/work/src,tt_um_chip_rom,wokwi,flow completed,0h0m46s0ms,0h0m30s0ms,2673.391732090503,0.01795472,1336.6958660452515,0.57,2.25307,483.72,24,0,0,0,0,0,0,0,0,0,0,-1,-1,80,96,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,109715.0,0.0,0.0,0.06,0.04,0.0,-1,8,43,8,43,0,0,0,0,0,0,0,0,0,0,0,0,-1,-1,-1,1239,225,0,244,24,1732,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,26.520,38.870,0.3,1,10,0.6,0,sky130_fd_sc_hd,AREA 0
+/work/src,tt_um_chip_rom,wokwi,flow completed,0h0m44s0ms,0h0m30s0ms,2673.391732090503,0.01795472,1336.6958660452515,0.57,2.25307,484.09,24,0,0,0,0,0,0,0,0,0,0,-1,-1,80,96,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,109715.0,0.0,0.0,0.06,0.04,0.0,-1,8,43,8,43,0,0,0,0,0,0,0,0,0,0,0,0,-1,-1,-1,1239,225,0,244,24,1732,16493.3184,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,26.520,38.870,0.3,1,10,0.6,0,sky130_fd_sc_hd,AREA 0