feat: update project tt_um_wokwi_380416099936681985 from honnet/TinyT…

…apeout_tt05-submission-template

Commit: 16d9c0f7ce26c4b637606b988ec1d25415c3ca51
Workflow: https://github.com/honnet/TinyTapeout_tt05-submission-template/actions/runs/6751223706

projects/tt_um_wokwi_380416099936681985/commit_id.json

@@ -1,8 +1,8 @@
 {
   "app": "Tiny Tapeout tt05 98e7cb27",
   "repo": "https://github.com/honnet/TinyTapeout_tt05-submission-template",
-  "commit": "aa5161c3a26d9ffc2d9da43d21d1d45322baae2e",
-  "workflow_url": "https://github.com/honnet/TinyTapeout_tt05-submission-template/actions/runs/6750941538",
+  "commit": "16d9c0f7ce26c4b637606b988ec1d25415c3ca51",
+  "workflow_url": "https://github.com/honnet/TinyTapeout_tt05-submission-template/actions/runs/6751223706",
   "sort_id": 1699052301501,
   "openlane_version": "OpenLane 7e5a2e9fb274c0a100b4859a927adce7089455ff",
   "power_gate": false

projects/tt_um_wokwi_380416099936681985/info.yaml

@@ -1,14 +1,14 @@
---- 
+---
 # Tiny Tapeout project information
 project:
-  wokwi_id:    380416099936681985        # If using wokwi, set this to your project's ID
+  wokwi_id:    0        # If using wokwi, set this to your project's ID
 
-# If using an HDL, set wokwi_id as 0 and uncomment and list your source files here. 
+# If using an HDL, set wokwi_id as 0 and uncomment and list your source files here.
 # Source files must be in ./src and you must list each source file separately
-#  source_files:        
-#    - counter.v
-#    - decoder.v
-#  top_module:  "tt_um_example"      # Put the name of your top module here, must start with "tt_um_". Make it unique by including your github username
+  source_files:
+    - tt_um_wokwi_380416099936681985.v
+    - decoder.v
+  top_module:  "tt_um_wokwi_380416099936681985"      # Put the name of your top module here, must start with "tt_um_". Make it unique by including your github username
 
 # How many tiles your design occupies? A single tile is about 167x108 uM.
   tiles: "1x1"    # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2 or 8x2
@@ -20,30 +20,41 @@ yaml_version: 4
 # it does and how to operate it. This info will be automatically collected and used to make a datasheet for the chip.
 #
 # Here is a great example: https://github.com/davidsiaw/tt02-davidsiaw-stackcalc/blob/38c5647f83aad2aec675d566aa3d67b98f0aac81/info.yaml
-documentation: 
-  author:       "honnet"      # Your name
-  title:        "Half Adder"      # Project title
-  language:     "Wokwi" # other examples include Verilog, Amaranth, VHDL, etc
-  description:  "Half Adder"      # Short description of what your project does
+documentation:
+  author:       "Matt Venn, cloned by Cedric Honnet"      # Your name
+  title:        "7 segment seconds (Verilog Demo)"      # Project title
+  language:     "Verilog" # other examples include Verilog, Amaranth, VHDL, etc
+  description:  "Count up to 10, one second at a time."      # Short description of what your project does
 
 # Longer description of how the project works. You can use standard markdown format.
   how_it_works: |
-      Explain how your project works
+      Uses a set of registers to divide the clock, and then some combinational logic
+      to convert from binary to decimal for the display.
+
+      Puts the bottom 8 bits of the counter on the bidirectional outputs.
+
+      With all the inputs set to 0, the internal 24 bit compare is set to 10,000,000. This means the
+      counter will increment by one each second.
+
+      If any inputs are non zero, then the input will be used as an bits 11 to 18 of the 24 bit compare register.
+      Example: setting the inputs to 00010000 will program 16384 into the compare register.
+      With a 10MHz clock the counter will increment ~610 times per second.
 
 # Instructions on how someone could test your project, include things like what buttons do what and how to set the clock if needed
   how_to_test:  |
-      Explain how to test your project
+      After reset, the counter should increase by one every second with a 10MHz input clock.
+      Experiment by changing the inputs to change the counting speed.
 
 # A description of what the inputs do (e.g. red button, SPI CLK, SPI MOSI, etc).
-  inputs:               
-    - none
-    - none
-    - none
-    - none
-    - none
-    - none
-    - none
-    - none
+  inputs:
+    - compare bit 11
+    - compare bit 12
+    - compare bit 13
+    - compare bit 14
+    - compare bit 15
+    - compare bit 16
+    - compare bit 17
+    - compare bit 18
 # A description of what the outputs do (e.g. status LED, SPI MISO, etc)
   outputs:
     - segment a
@@ -56,19 +67,19 @@ documentation:
     - dot
 # A description of what the bidirectional I/O pins do (e.g. I2C SDA, I2C SCL, etc)
   bidirectional:
-    - none
-    - none
-    - none
-    - none
-    - none
-    - none
-    - none
-    - none
+    - second counter bit 0
+    - second counter bit 1
+    - second counter bit 2
+    - second counter bit 3
+    - second counter bit 4
+    - second counter bit 5
+    - second counter bit 6
+    - second counter bit 7
 
 # The following fields are optional
-  tag:          ""      # comma separated list of tags: test, encryption, experiment, clock, animation, utility, industrial, pwm, fpga, alu, microprocessor, risc, riscv, sensor, signal generator, fft, filter, music, bcd, sound, serial, timer, random number generator, calculator, decoder, counter, puzzle, multiplier, game, oscillator,
+  tag:          "timer, test"      # comma separated list of tags: test, encryption, experiment, clock, animation, utility, industrial, pwm, fpga, alu, microprocessor, risc, riscv, sensor, signal generator, fft, filter, music, bcd, sound, serial, timer, random number generator, calculator, decoder, counter, puzzle, multiplier, game, oscillator,
   external_hw:  ""      # Describe any external hardware needed
-  discord:      ""      # Your discord handle, used for communication and automatically assigning tapeout role after a submission
+  discord:      "mattvenn"      # Your discord handle, used for communication and automatically assigning tapeout role after a submission
   doc_link:     ""      # URL to longer form documentation, eg the README.md in your repository
-  clock_hz:     0       # Clock frequency in Hz (if required)
+  clock_hz:     10000000       # Clock frequency in Hz (if required)
   picture:      ""      # relative path to a picture in your repository (must be 512kb or less)

projects/tt_um_wokwi_380416099936681985/metrics.csv

@@ -1,2 +1,2 @@
 design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,MAX_FANOUT_CONSTRAINT,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_STRATEGY
-/work/src,tt_um_wokwi_380416099936681985,wokwi,flow completed,0h1m37s0ms,0h1m17s0ms,3728.261466087052,0.0187755072,1864.130733043526,0.77,-1,494.37,27,0,0,0,0,0,0,0,0,0,0,-1,-1,514,180,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,508359.0,0.0,1.44,0.37,0.0,0.0,-1,29,64,29,64,0,0,0,2,1,0,0,0,0,1,0,0,2,2,2,1295,246,0,255,35,1831,17274.0672,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,26.520,40.710,0.3,1,10,0.6,0,sky130_fd_sc_hd,AREA 0
+/work/src,tt_um_wokwi_380416099936681985,wokwi,flow completed,0h1m28s0ms,0h1m10s0ms,26097.830262609365,0.0187755072,13048.915131304682,12.97,-1,528.25,221,0,0,0,0,0,0,0,0,0,0,-1,-1,4297,1564,0.0,-1,-1,-1,-1,0.0,-1,-1,-1,-1,3185463.0,0.0,9.48,5.75,0.23,0.0,-1,155,306,14,113,0,0,0,204,14,7,16,5,44,39,0,20,37,35,12,1179,246,0,302,245,1972,17274.0672,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,21.0,47.61904761904762,20,1,50,26.520,40.710,0.3,1,10,0.6,0,sky130_fd_sc_hd,AREA 0

projects/tt_um_wokwi_380416099936681985/synthesis-stats.txt

@@ -3,19 +3,55 @@
 
 === tt_um_wokwi_380416099936681985 ===
 
-   Number of wires:                 11
-   Number of wire bits:             46
-   Number of public wires:          10
-   Number of public wire bits:      45
+   Number of wires:                205
+   Number of wire bits:            240
+   Number of public wires:          36
+   Number of public wire bits:      71
    Number of memories:               0
    Number of memory bits:            0
    Number of processes:              0
-   Number of cells:                 27
-     sky130_fd_sc_hd__and2_2         1
-     sky130_fd_sc_hd__buf_1          1
+   Number of cells:                221
+     sky130_fd_sc_hd__a2111o_2       3
+     sky130_fd_sc_hd__a211o_2        2
+     sky130_fd_sc_hd__a21bo_2        1
+     sky130_fd_sc_hd__a21boi_2       1
+     sky130_fd_sc_hd__a21o_2         7
+     sky130_fd_sc_hd__a21oi_2        7
+     sky130_fd_sc_hd__a2bb2o_2       1
+     sky130_fd_sc_hd__a2bb2oi_2      1
+     sky130_fd_sc_hd__a31o_2         6
+     sky130_fd_sc_hd__and2_2         3
+     sky130_fd_sc_hd__and2b_2        9
+     sky130_fd_sc_hd__and3_2        11
+     sky130_fd_sc_hd__and3b_2       10
+     sky130_fd_sc_hd__and4_2         8
+     sky130_fd_sc_hd__and4b_2        1
+     sky130_fd_sc_hd__buf_1         21
      sky130_fd_sc_hd__buf_2          8
-     sky130_fd_sc_hd__conb_1        16
+     sky130_fd_sc_hd__conb_1         9
+     sky130_fd_sc_hd__dfxtp_2       35
+     sky130_fd_sc_hd__inv_2         12
+     sky130_fd_sc_hd__mux2_2         3
+     sky130_fd_sc_hd__nand2_2       11
+     sky130_fd_sc_hd__nand3_2        3
+     sky130_fd_sc_hd__nor2_2        11
+     sky130_fd_sc_hd__nor4_2         3
+     sky130_fd_sc_hd__o211a_2        4
+     sky130_fd_sc_hd__o21a_2         3
+     sky130_fd_sc_hd__o21ai_2        3
+     sky130_fd_sc_hd__o21ba_2        1
+     sky130_fd_sc_hd__o21bai_2       1
+     sky130_fd_sc_hd__o221a_2        2
+     sky130_fd_sc_hd__o22a_2         1
+     sky130_fd_sc_hd__o2bb2a_2       1
+     sky130_fd_sc_hd__o31a_2         1
+     sky130_fd_sc_hd__o32a_2         1
+     sky130_fd_sc_hd__or2_2          6
+     sky130_fd_sc_hd__or2b_2         3
+     sky130_fd_sc_hd__or3_2          1
+     sky130_fd_sc_hd__or4_2          3
+     sky130_fd_sc_hd__xnor2_2        2
      sky130_fd_sc_hd__xor2_2         1
 
-   Chip area for module '\tt_um_wokwi_380416099936681985': 127.622400
+   Chip area for module '\tt_um_wokwi_380416099936681985': 2162.073600
 

projects/tt_um_wokwi_380416099936681985/tt_um_wokwi_380416099936681985.lef

@@ -50,6 +50,7 @@ MACRO tt_um_wokwi_380416099936681985
   PIN clk
     DIRECTION INPUT ;
     USE SIGNAL ;
+    ANTENNAGATEAREA 0.852000 ;
     PORT
       LAYER met4 ;
         RECT 145.670 110.520 145.970 111.520 ;
@@ -66,6 +67,7 @@ MACRO tt_um_wokwi_380416099936681985
   PIN rst_n
     DIRECTION INPUT ;
     USE SIGNAL ;
+    ANTENNAGATEAREA 0.159000 ;
     PORT
       LAYER met4 ;
         RECT 142.910 110.520 143.210 111.520 ;
@@ -274,6 +276,7 @@ MACRO tt_um_wokwi_380416099936681985
   PIN uio_out[0]
     DIRECTION OUTPUT TRISTATE ;
     USE SIGNAL ;
+    ANTENNADIFFAREA 0.445500 ;
     PORT
       LAYER met4 ;
         RECT 73.910 110.520 74.210 111.520 ;
@@ -282,6 +285,7 @@ MACRO tt_um_wokwi_380416099936681985
   PIN uio_out[1]
     DIRECTION OUTPUT TRISTATE ;
     USE SIGNAL ;
+    ANTENNADIFFAREA 0.445500 ;
     PORT
       LAYER met4 ;
         RECT 71.150 110.520 71.450 111.520 ;
@@ -290,6 +294,7 @@ MACRO tt_um_wokwi_380416099936681985
   PIN uio_out[2]
     DIRECTION OUTPUT TRISTATE ;
     USE SIGNAL ;
+    ANTENNADIFFAREA 0.445500 ;
     PORT
       LAYER met4 ;
         RECT 68.390 110.520 68.690 111.520 ;
@@ -298,6 +303,7 @@ MACRO tt_um_wokwi_380416099936681985
   PIN uio_out[3]
     DIRECTION OUTPUT TRISTATE ;
     USE SIGNAL ;
+    ANTENNADIFFAREA 0.445500 ;
     PORT
       LAYER met4 ;
         RECT 65.630 110.520 65.930 111.520 ;
@@ -306,6 +312,7 @@ MACRO tt_um_wokwi_380416099936681985
   PIN uio_out[4]
     DIRECTION OUTPUT TRISTATE ;
     USE SIGNAL ;
+    ANTENNADIFFAREA 0.445500 ;
     PORT
       LAYER met4 ;
         RECT 62.870 110.520 63.170 111.520 ;
@@ -314,6 +321,7 @@ MACRO tt_um_wokwi_380416099936681985
   PIN uio_out[5]
     DIRECTION OUTPUT TRISTATE ;
     USE SIGNAL ;
+    ANTENNADIFFAREA 0.795200 ;
     PORT
       LAYER met4 ;
         RECT 60.110 110.520 60.410 111.520 ;
@@ -322,6 +330,7 @@ MACRO tt_um_wokwi_380416099936681985
   PIN uio_out[6]
     DIRECTION OUTPUT TRISTATE ;
     USE SIGNAL ;
+    ANTENNADIFFAREA 0.445500 ;
     PORT
       LAYER met4 ;
         RECT 57.350 110.520 57.650 111.520 ;
@@ -330,6 +339,7 @@ MACRO tt_um_wokwi_380416099936681985
   PIN uio_out[7]
     DIRECTION OUTPUT TRISTATE ;
     USE SIGNAL ;
+    ANTENNADIFFAREA 0.795200 ;
     PORT
       LAYER met4 ;
         RECT 54.590 110.520 54.890 111.520 ;
@@ -338,7 +348,7 @@ MACRO tt_um_wokwi_380416099936681985
   PIN uo_out[0]
     DIRECTION OUTPUT TRISTATE ;
     USE SIGNAL ;
-    ANTENNADIFFAREA 0.795200 ;
+    ANTENNADIFFAREA 0.445500 ;
     PORT
       LAYER met4 ;
         RECT 95.990 110.520 96.290 111.520 ;
@@ -347,7 +357,7 @@ MACRO tt_um_wokwi_380416099936681985
   PIN uo_out[1]
     DIRECTION OUTPUT TRISTATE ;
     USE SIGNAL ;
-    ANTENNADIFFAREA 0.795200 ;
+    ANTENNADIFFAREA 0.445500 ;
     PORT
       LAYER met4 ;
         RECT 93.230 110.520 93.530 111.520 ;
@@ -365,7 +375,7 @@ MACRO tt_um_wokwi_380416099936681985
   PIN uo_out[3]
     DIRECTION OUTPUT TRISTATE ;
     USE SIGNAL ;
-    ANTENNADIFFAREA 0.795200 ;
+    ANTENNADIFFAREA 0.445500 ;
     PORT
       LAYER met4 ;
         RECT 87.710 110.520 88.010 111.520 ;
@@ -383,7 +393,7 @@ MACRO tt_um_wokwi_380416099936681985
   PIN uo_out[5]
     DIRECTION OUTPUT TRISTATE ;
     USE SIGNAL ;
-    ANTENNADIFFAREA 0.795200 ;
+    ANTENNADIFFAREA 0.445500 ;
     PORT
       LAYER met4 ;
         RECT 82.190 110.520 82.490 111.520 ;
@@ -392,7 +402,7 @@ MACRO tt_um_wokwi_380416099936681985
   PIN uo_out[6]
     DIRECTION OUTPUT TRISTATE ;
     USE SIGNAL ;
-    ANTENNADIFFAREA 0.795200 ;
+    ANTENNADIFFAREA 0.445500 ;
     PORT
       LAYER met4 ;
         RECT 79.430 110.520 79.730 111.520 ;
@@ -401,7 +411,6 @@ MACRO tt_um_wokwi_380416099936681985
   PIN uo_out[7]
     DIRECTION OUTPUT TRISTATE ;
     USE SIGNAL ;
-    ANTENNADIFFAREA 0.795200 ;
     PORT
       LAYER met4 ;
         RECT 76.670 110.520 76.970 111.520 ;
@@ -432,9 +441,9 @@ MACRO tt_um_wokwi_380416099936681985
       LAYER li1 ;
         RECT 2.760 2.635 165.600 108.885 ;
       LAYER met1 ;
-        RECT 2.760 2.480 166.400 110.800 ;
+        RECT 2.760 2.480 166.400 109.040 ;
       LAYER met2 ;
-        RECT 22.345 2.535 166.370 110.830 ;
+        RECT 22.345 2.535 166.370 110.005 ;
       LAYER met3 ;
         RECT 22.325 2.555 166.390 109.985 ;
       LAYER met4 ;
@@ -477,13 +486,17 @@ MACRO tt_um_wokwi_380416099936681985
         RECT 132.570 110.120 134.230 111.170 ;
         RECT 135.330 110.120 136.990 111.170 ;
         RECT 138.090 110.120 139.750 111.170 ;
-        RECT 32.495 109.440 140.465 110.120 ;
-        RECT 32.495 107.615 42.270 109.440 ;
-        RECT 44.670 107.615 62.625 109.440 ;
-        RECT 65.025 107.615 82.980 109.440 ;
-        RECT 85.380 107.615 103.335 109.440 ;
-        RECT 105.735 107.615 123.690 109.440 ;
-        RECT 126.090 107.615 140.465 109.440 ;
+        RECT 140.850 110.120 142.510 111.170 ;
+        RECT 143.610 110.120 145.270 111.170 ;
+        RECT 146.370 110.120 146.905 111.170 ;
+        RECT 32.495 109.440 146.905 110.120 ;
+        RECT 32.495 96.055 42.270 109.440 ;
+        RECT 44.670 96.055 62.625 109.440 ;
+        RECT 65.025 96.055 82.980 109.440 ;
+        RECT 85.380 96.055 103.335 109.440 ;
+        RECT 105.735 96.055 123.690 109.440 ;
+        RECT 126.090 96.055 144.045 109.440 ;
+        RECT 146.445 96.055 146.905 109.440 ;
   END
 END tt_um_wokwi_380416099936681985
 END LIBRARY